On rv32 targets, vwsll_zext1_scalar_<mode> would trigger an ice in maybe_legitimize_instruction when zero extending a uint32 to uint64 due to a mismatch between the input operand's mode (DI) and the expanded insn operand's mode (Pmode == SI). Ensure that mode of the operands match
gcc/ChangeLog: * config/riscv/autovec-opt.md: Fix mode mismatch Signed-off-by: Edwin Lu <e...@rivosinc.com> Co-authored-by: Robin Dapp <rd...@ventanamicro.com> --- gcc/config/riscv/autovec-opt.md | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 6a2eabbd854..b9e5ccfef25 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -1519,6 +1519,7 @@ (define_insn_and_split "*vwsll_zext1_scalar_<mode>" { if (GET_CODE (operands[2]) == SUBREG) operands[2] = SUBREG_REG (operands[2]); + operands[2] = gen_lowpart (Pmode, operands[2]); insn_code icode = code_for_pred_vwsll_scalar (<MODE>mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); DONE; -- 2.34.1