This is a hold-over from GCN3 where v_add always wrote to the condition
register, whether you wanted it or not. This hasn't been true since GCN5, and
we dropped support for GCN3 a little while ago, so let's fix it.
There was actually a latent bug here because some other post-reload splitters
were generating v_add instructions without declaring the VCC clobber (at least
mul did this), so this should fix some wrong-code bugs also.
gcc/ChangeLog:
* config/gcn/gcn-valu.md (add<mode>3<exec_clobber>): Rename ...
(add<mode>3<exec>): ... to this, remove the clobber, and change the
instruction from v_add_co_u32 to v_add_u32.
(add<mode>3_dup<exec_clobber>): Rename ...
(add<mode>3_dup<exec>): ... to this, and likewise.
(sub<mode>3<exec_clobber>): Rename ...
(sub<mode>3<exec>): ... to this, and likewise
* config/gcn/gcn.md (addsi3): Remove the DI clobber, and change the
instruction from v_add_co_u32 to v_add_u32.
(addsi3_scc): Likewise.
(subsi3): Likewise, but for v_sub_co_u32.
(muldi3): Likewise.
---
gcc/config/gcn/gcn-valu.md | 23 ++++++++++-------------
gcc/config/gcn/gcn.md | 28 +++++++++++-----------------
2 files changed, 21 insertions(+), 30 deletions(-)
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 4b21302e82c..f49c1ed0b6d 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -1455,28 +1455,26 @@ (define_insn "@dpp_distribute_odd<mode>"
;; }}}
;; {{{ ALU special case: add/sub
-(define_insn "add<mode>3<exec_clobber>"
+(define_insn "add<mode>3<exec>"
[(set (match_operand:V_INT_1REG 0 "register_operand")
(plus:V_INT_1REG
(match_operand:V_INT_1REG 1 "register_operand")
- (match_operand:V_INT_1REG 2 "gcn_alu_operand")))
- (clobber (reg:DI VCC_REG))]
+ (match_operand:V_INT_1REG 2 "gcn_alu_operand")))]
""
{@ [cons: =0, %1, 2; attrs: type, length]
- [v,v,vSvA;vop2,4] v_add_co_u32\t%0, vcc, %2, %1
+ [v,v,vSvA;vop2,4] {v_add_u32|v_add_nc_u32}\t%0, %2, %1
[v,v,vSvB;vop2,8] ^
})
-(define_insn "add<mode>3_dup<exec_clobber>"
+(define_insn "add<mode>3_dup<exec>"
[(set (match_operand:V_INT_1REG 0 "register_operand")
(plus:V_INT_1REG
(vec_duplicate:V_INT_1REG
(match_operand:<SCALAR_MODE> 2 "gcn_alu_operand"))
- (match_operand:V_INT_1REG 1 "register_operand")))
- (clobber (reg:DI VCC_REG))]
+ (match_operand:V_INT_1REG 1 "register_operand")))]
""
{@ [cons: =0, 1, 2; attrs: type, length]
- [v,v,SvA;vop2,4] v_add_co_u32\t%0, vcc, %2, %1
+ [v,v,SvA;vop2,4] {v_add_u32|v_add_nc_u32}\t%0, %2, %1
[v,v,SvB;vop2,8] ^
})
@@ -1551,16 +1549,15 @@ (define_insn "addc<mode>3<exec_vcc>"
[(set_attr "type" "vop2,vop3b")
(set_attr "length" "4,8")])
-(define_insn "sub<mode>3<exec_clobber>"
+(define_insn "sub<mode>3<exec>"
[(set (match_operand:V_INT_1REG 0 "register_operand" "= v, v")
(minus:V_INT_1REG
(match_operand:V_INT_1REG 1 "gcn_alu_operand" "vSvB, v")
- (match_operand:V_INT_1REG 2 "gcn_alu_operand" " v,vSvB")))
- (clobber (reg:DI VCC_REG))]
+ (match_operand:V_INT_1REG 2 "gcn_alu_operand" " v,vSvB")))]
""
"@
- v_sub_co_u32\t%0, vcc, %1, %2
- v_subrev_co_u32\t%0, vcc, %2, %1"
+ {v_sub_u32|v_sub_nc_u32}\t%0, %1, %2
+ {v_subrev_u32|v_subrev_nc_u32}\t%0, %2, %1"
[(set_attr "type" "vop2")
(set_attr "length" "8,8")])
diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md
index 2ce2e054fbf..9193461ed49 100644
--- a/gcc/config/gcn/gcn.md
+++ b/gcc/config/gcn/gcn.md
@@ -1136,14 +1136,13 @@ (define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "= Sg, Sg, Sg, v")
(plus:SI (match_operand:SI 1 "gcn_alu_operand" "%SgA, 0,SgA, v")
(match_operand:SI 2 "gcn_alu_operand" " SgA,SgJ, B,vBSv")))
- (clobber (match_scratch:BI 3 "= cs, cs, cs,
X"))
- (clobber (match_scratch:DI 4 "= X, X, X,
cV"))]
+ (clobber (match_scratch:BI 3 "= cs, cs, cs,
X"))]
""
"@
s_add_i32\t%0, %1, %2
s_addk_i32\t%0, %2
s_add_i32\t%0, %1, %2
- v_add_co_u32\t%0, vcc, %2, %1"
+ {v_add_u32|v_add_nc_u32}\t%0, %2, %1"
[(set_attr "type" "sop2,sopk,sop2,vop2")
(set_attr "length" "4,4,8,8")])
@@ -1151,8 +1150,7 @@ (define_expand "addsi3_scc"
[(parallel [(set (match_operand:SI 0 "register_operand")
(plus:SI (match_operand:SI 1 "gcn_alu_operand")
(match_operand:SI 2 "gcn_alu_operand")))
- (clobber (reg:BI SCC_REG))
- (clobber (scratch:DI))])]
+ (clobber (reg:BI SCC_REG))])]
""
{})
@@ -1332,14 +1330,13 @@ (define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=Sg, Sg, v, v")
(minus:SI (match_operand:SI 1 "gcn_alu_operand" "SgA,SgA, v,vBSv")
(match_operand:SI 2 "gcn_alu_operand" "SgA, B, vBSv, v")))
- (clobber (match_scratch:BI 3 "=cs, cs, X,
X"))
- (clobber (match_scratch:DI 4 "= X, X, cV,
cV"))]
+ (clobber (match_scratch:BI 3 "=cs, cs, X,
X"))]
""
"@
s_sub_i32\t%0, %1, %2
s_sub_i32\t%0, %1, %2
- v_subrev_co_u32\t%0, vcc, %2, %1
- v_sub_co_u32\t%0, vcc, %1, %2"
+ {v_subrev_u32|v_subrev_nc_u32}\t%0, %2, %1
+ {v_sub_u32|v_sub_nc_u32}\t%0, %1, %2"
[(set_attr "type" "sop2,sop2,vop2,vop2")
(set_attr "length" "4,8,8,8")])
@@ -1569,8 +1566,7 @@ (define_insn_and_split "muldi3"
(mult:DI (match_operand:DI 1 "register_operand" "%Sg, Sg, v, v")
(match_operand:DI 2 "nonmemory_operand" "Sg, i,vSv, A")))
(clobber (match_scratch:SI 3 "=&Sg,&Sg,&v,&v"))
- (clobber (match_scratch:BI 4 "=cs, cs, X, X"))
- (clobber (match_scratch:DI 5 "=X, X,cV,cV"))]
+ (clobber (match_scratch:BI 4 "=cs, cs, X, X"))]
""
"#"
"reload_completed"
@@ -1585,15 +1581,13 @@ (define_insn_and_split "muldi3"
emit_insn (gen_umulsidi3 (operands[0], op1lo, op2lo));
emit_insn (gen_mulsi3 (tmp, op1lo, op2hi));
rtx add = gen_rtx_SET (dsthi, gen_rtx_PLUS (SImode, dsthi, tmp));
- rtx clob1 = gen_rtx_CLOBBER (VOIDmode, operands[4]);
- rtx clob2 = gen_rtx_CLOBBER (VOIDmode, operands[5]);
- add = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3, add, clob1, clob2));
+ rtx clob = gen_rtx_CLOBBER (VOIDmode, operands[4]);
+ add = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, add, clob));
emit_insn (add);
emit_insn (gen_mulsi3 (tmp, op1hi, op2lo));
add = gen_rtx_SET (dsthi, gen_rtx_PLUS (SImode, dsthi, tmp));
- clob1 = gen_rtx_CLOBBER (VOIDmode, operands[4]);
- clob2 = gen_rtx_CLOBBER (VOIDmode, operands[5]);
- add = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3, add, clob1, clob2));
+ clob = gen_rtx_CLOBBER (VOIDmode, operands[4]);
+ add = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, add, clob));
emit_insn (add);
DONE;
})
--
2.50.0
