[PATCH] aarch64: PR target/121749: Use correct predicate for narrowing shift amounts

[Kyrylo Tkachov]

Hi all,

With g:d20b2ad845876eec0ee80a3933ad49f9f6c4ee30 the narrowing shift instructions
are now represented with standard RTL and more merging optimisations occur.
This exposed a wrong predicate for the shift amount operand.
The shift amount is the number of bits of the narrow destination, not the input
sources.
Correct this by using the vn_mode attribute when specifying the predicate, which
exists for this purpose.

I've spotted a few more narrowing shift patterns that need the restriction, so
they are updated as well.

Bootstrapped and tested on aarch64-none-linux-gnu.

Ok for trunk?
Thanks,
Kyrill

Signed-off-by: Kyrylo Tkachov <ktkac...@nvidia.com>

gcc/

        PR target/121749
        * config/aarch64/aarch64-simd.md (aarch64_<shrn_op>shrn_n<mode>):
        Use aarch64_simd_shift_imm_offset_<vn_mode> instead of
        aarch64_simd_shift_imm_offset_<ve_mode> predicate.
        (aarch64_<shrn_op>shrn_n<mode> VQN define_expand): Likewise.
        (*aarch64_<shrn_op>rshrn_n<mode>_insn): Likewise.
        (aarch64_<shrn_op>rshrn_n<mode>): Likewise.
        (aarch64_<shrn_op>rshrn_n<mode> VQN define_expand): Likewise.
        (aarch64_sqshrun_n<mode>_insn): Likewise.
        (aarch64_sqshrun_n<mode>): Likewise.
        (aarch64_sqshrun_n<mode> VQN define_expand): Likewise.
        (aarch64_sqrshrun_n<mode>_insn): Likewise.
        (aarch64_sqrshrun_n<mode>): Likewise.
        (aarch64_sqrshrun_n<mode>): Likewise.
        * config/aarch64/iterators.md (vn_mode): Handle DI, SI, HI modes.

gcc/testsuite/

        PR target/121749
        * gcc.target/aarch64/simd/pr121749.c: New test.

0001-aarch64-PR-target-121749-Use-correct-predicate-for-n.patch
Description: 0001-aarch64-PR-target-121749-Use-correct-predicate-for-n.patch