The MIPS Allegrex CPU features a vector floating point coprocessor.
Signed-off-by: David Guillen Fandos <[email protected]>
---
gas/testsuite/gas/mips/allegrex-vfpu.d | 15 +++++++++++++++
gas/testsuite/gas/mips/allegrex-vfpu.s | 13 +++++++++++++
gas/testsuite/gas/mips/mips.exp | 1 +
opcodes/mips-opc.c | 10 +++++++++-
4 files changed, 38 insertions(+), 1 deletion(-)
create mode 100644 gas/testsuite/gas/mips/allegrex-vfpu.d
create mode 100644 gas/testsuite/gas/mips/allegrex-vfpu.s
diff --git a/gas/testsuite/gas/mips/allegrex-vfpu.d
b/gas/testsuite/gas/mips/allegrex-vfpu.d
new file mode 100644
index 00000000000..be6554c825e
--- /dev/null
+++ b/gas/testsuite/gas/mips/allegrex-vfpu.d
@@ -0,0 +1,15 @@
+#as: -march=allegrex -mabi=32
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: Sony Allegrex VFPU tests
+
+.*: file format .*
+
+
+Disassembly of section .text:
+0x00000000 ffff0000 vnop
+0x00000004 ffff0320 vsync
+0x00000008 ffff040d vflush
+0x0000000c ffff007b vsync 0x7b
+0x00000010 ffff0320 vsync
+0x00000014 ffff040d vflush
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/allegrex-vfpu.s
b/gas/testsuite/gas/mips/allegrex-vfpu.s
new file mode 100644
index 00000000000..ca01c2b3a47
--- /dev/null
+++ b/gas/testsuite/gas/mips/allegrex-vfpu.s
@@ -0,0 +1,13 @@
+ .text
+ .set noreorder
+
+ vnop
+ vsync
+ vflush
+ vsync 123
+ vsync 800
+ vsync 1037
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 4ae4a48e286..15aabc44e2a 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1713,6 +1713,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "allegrex"
run_dump_test "allegrex-removed"
+ run_dump_test "allegrex-vfpu"
run_list_test_arches "ext-ill" [mips_arch_list_matching mips64r2]
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 1d7d72ae0a7..223fb89de19 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -635,7 +635,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"vmulax", "+m+K,+6+K,+7+N", 0x4a0001bc, 0xfe0007ff, CP,
VU0CH, VU0, 0, 0 },
{"vmulay", "+m+K,+6+K,+7+N", 0x4a0001bd, 0xfe0007ff, CP,
VU0CH, VU0, 0, 0 },
{"vmulaz", "+m+K,+6+K,+7+N", 0x4a0001be, 0xfe0007ff, CP,
VU0CH, VU0, 0, 0 },
-{"vnop", "", 0x4a0002ff, 0xffffffff, CP,
0, VU0, 0, 0 },
{"vopmula.xyz", "+m+K,+6+K,+7+K", 0x4bc002fe, 0xffe007ff,
CP, 0, VU0, 0, 0 },
{"vopmula", "+m+K,+6+K,+7+K", 0x4bc002fe, 0xffe007ff, CP,
0, VU0, 0, 0 },
{"vopmsub.xyz", "+5+K,+6+K,+7+K", 0x4bc0002e, 0xffe0003f,
CP, 0, VU0, 0, 0 },
@@ -664,6 +663,15 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"vsubaz", "+m+K,+6+K,+7+N", 0x4a00007e, 0xfe0007ff, CP,
VU0CH, VU0, 0, 0 },
{"vwaitq", "", 0x4a0003bf, 0xffffffff, CP,
0, VU0, 0, 0 },
+/* Shared/repeated opcodes. */
+{"vnop", "", 0x4a0002ff, 0xffffffff, CP,
0, VU0, 0, 0 },
+{"vnop", "", 0xffff0000, 0xffffffff, CP,
0, ALX, 0, 0 },
+
+/* Allegrex VFPU coprocessor. Redefines coprocessor 2 and 3 (and other unused
opcodes). */
+{"vflush", "", 0xffff040d, 0xffffffff, CP,
0, ALX, 0, 0 },
+{"vsync", "", 0xffff0320, 0xffffffff, CP,
0, ALX, 0, 0 },
+{"vsync", "i", 0xffff0000, 0xffff0000, CP,
0, ALX, 0, 0 },
+
{"abs", "d,v", 0, (int) M_ABS,
INSN_MACRO, 0, I1, 0, 0 },
{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_1|RD_2|FP_S,
0, I1, 0, 0 },
{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_1|RD_2|FP_D,
0, I1, 0, SF },
--
2.51.1
