Some VFPU instructions do not support prefixes on certain registers. The operands are therefore decorated and checked accordingly at match time. Some prefixes are allowed though.
Add more VFPU vector instructions with prefix compatibility decorators. Signed-off-by: David Guillen Fandos <[email protected]> --- gas/config/tc-mips.c | 35 +++- gas/testsuite/gas/mips/allegrex-vfpu-errors.l | 12 ++ gas/testsuite/gas/mips/allegrex-vfpu-errors.s | 12 ++ gas/testsuite/gas/mips/allegrex-vfpu.d | 49 ++++++ gas/testsuite/gas/mips/allegrex-vfpu.s | 43 +++++ include/opcode/mips.h | 15 ++ opcodes/mips-dis.c | 4 +- opcodes/mips-formats.h | 32 ++-- opcodes/mips-opc.c | 150 +++++++++++------- 9 files changed, 276 insertions(+), 76 deletions(-) diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index eda2b641b80..930edceb6ec 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -4097,7 +4097,7 @@ validate_mips_insn (const struct mips_opcode *opcode, if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) ++s; if (decode_operand && (*s == '?')) - s += 2; + s += 3; opno += 1; break; @@ -6823,7 +6823,7 @@ match_vu0_suffix_operand (struct mips_arg_info *arg, static bfd_boolean calculate_vfpu_prefix_imm (struct mips_arg_info *arg, enum mips_vfpu_reg_type regtype, unsigned int rsize, - unsigned int *immediate) + bool lim_pfx, unsigned int *immediate) { unsigned int i; unsigned imm24 = 0; @@ -6847,6 +6847,12 @@ calculate_vfpu_prefix_imm (struct mips_arg_info *arg, _("invalid destination prefix (can only contain masking/saturation)")); return false; } + if (lim_pfx && (pfxchan[i] & 0x3)) + { + set_insn_error (arg->argnum, + _("invalid destination prefix (only masking allowed)")); + return false; + } } else { @@ -6856,6 +6862,12 @@ calculate_vfpu_prefix_imm (struct mips_arg_info *arg, _("invalid source prefix (can only contain constant/swizzle/neg/abs)")); return false; } + if (lim_pfx && (pfxchan[i] & ~0x3)) + { + set_insn_error (arg->argnum, + _("invalid source prefix (only swizzle allowed)")); + return false; + } if (!(pfxchan[i] & 0x8) && (pfxchan[i] & 3) > rsize) { set_insn_error (arg->argnum, @@ -6887,7 +6899,7 @@ match_vfpu_prefix_operand (struct mips_arg_info *arg, regvfpuop = (struct mips_vfpu_reg_operand*)operand; if (!calculate_vfpu_prefix_imm (arg, regvfpuop->regtype, regvfpuop->rsize, - &imm24)) + false, &imm24)) return false; insn_insert_operand (arg->insn, operand, imm24); @@ -6942,9 +6954,11 @@ match_vfpu_reg_operand (struct mips_arg_info *arg, struct mips_opcode *pop; bfd_reloc_code_real_type unused_reloc[3] = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; + enum mips_vfpu_reg_type rtype = regvfpuop->regtype; - const char *pfxmemo = regvfpuop->regtype == OP_VFPU_REG_S ? "vpfxs" : - regvfpuop->regtype == OP_VFPU_REG_T ? "vpfxt" : "vpfxd"; + const char *pfxmemo = rtype == OP_VFPU_REG_S ? "vpfxs" : + rtype == OP_VFPU_REG_T ? "vpfxt" : "vpfxd"; + bool pfx_lim = regvfpuop->pfxcompat == OP_VFPU_PFXCOMPAT_LIMITED; if (regvfpuop->rsize + 1 != arg->token->u.pfx_vfpu.num_chs) { @@ -6952,12 +6966,19 @@ match_vfpu_reg_operand (struct mips_arg_info *arg, return false; } + if (regvfpuop->pfxcompat == OP_VFPU_PFXCOMPAT_NONE) + { + set_insn_error_ss(arg->argnum, "no prefixes allowed for %s-%s", + &pfxmemo[4], "register"); + return false; + } + /* Create a prefix instruction that precedes this one. */ pop = (struct mips_opcode *) str_hash_find (op_hash, pfxmemo); create_insn (&pfxinstr, pop); if (!calculate_vfpu_prefix_imm (arg, regvfpuop->regtype, regvfpuop->rsize, - &imm24)) + pfx_lim, &imm24)) return false; insn_insert_operand (&pfxinstr, decode_mips_operand (pop->args), imm24); @@ -9202,7 +9223,7 @@ match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, if (*args == '+' || *args == 'm' || *args == '-') args++; if (*args == '?') - args += 2; + args += 3; if (mips_optional_operand_p (operand) && args[1] == ',' diff --git a/gas/testsuite/gas/mips/allegrex-vfpu-errors.l b/gas/testsuite/gas/mips/allegrex-vfpu-errors.l index aa10cf49e75..497e7f8aed6 100644 --- a/gas/testsuite/gas/mips/allegrex-vfpu-errors.l +++ b/gas/testsuite/gas/mips/allegrex-vfpu-errors.l @@ -8,3 +8,15 @@ .*:10: Error: invalid VFPU prefix, expecting ',' or '\]' `vsub.s S000,S000,S000\[xx\]' .*:11: Error: invalid source prefix \(can only contain constant/swizzle/neg/abs\) `vsub.t R000,R000,R000\[m,m,\]' .*:12: Error: invalid destination prefix \(can only contain masking/saturation\) `vsub.t R000\[x,y,z\],R000,R000' +.*:13: Error: no prefixes allowed for s-register `vocp.q R000,R000\[x,x,x,x\]' +.*:14: Error: no prefixes allowed for d-register `vsat0.q R000\[m,,,\],R000' +.*:15: Error: no prefixes allowed for d-register `vsat1.q R000\[m,,,\],R000' +.*:16: Error: no prefixes allowed for d-register `vt4444.q R000\[m,\],R000' +.*:17: Error: no prefixes allowed for d-register `vt5551.q R000\[m,\],R000' +.*:18: Error: no prefixes allowed for d-register `vt5650.q R000\[m,\],R000' +.*:19: Error: invalid destination prefix \(only masking allowed\) `vi2us.q R000\[-1:1,-1:1\],R000' +.*:20: Error: invalid source prefix \(only swizzle allowed\) `vabs.q R000,R000\[|x|,x,x,x\]' +.*:21: Error: invalid source prefix \(only swizzle allowed\) `vabs.q R000,R000\[-x,x,x,x\]' +.*:22: Error: invalid source prefix \(only swizzle allowed\) `vabs.q R000,R000\[0,x,x,x\]' +.*:23: Error: invalid source prefix \(only swizzle allowed\) `vneg.q R000,R000\[0,x,x,x\]' +.*:24: Error: invalid source prefix \(only swizzle allowed\) `vt4444.q R000,R000\[-x,x,x,x\]' diff --git a/gas/testsuite/gas/mips/allegrex-vfpu-errors.s b/gas/testsuite/gas/mips/allegrex-vfpu-errors.s index c2fa6dda856..67024c61348 100644 --- a/gas/testsuite/gas/mips/allegrex-vfpu-errors.s +++ b/gas/testsuite/gas/mips/allegrex-vfpu-errors.s @@ -10,6 +10,18 @@ vsub.s S000, S000, S000[xx] vsub.t R000, R000, R000[m,m,] vsub.t R000[x,y,z], R000, R000 + vocp.q R000, R000[x,x,x,x] + vsat0.q R000[m,,,], R000 + vsat1.q R000[m,,,], R000 + vt4444.q R000[m,], R000 + vt5551.q R000[m,], R000 + vt5650.q R000[m,], R000 + vi2us.q R000[-1:1,-1:1], R000 + vabs.q R000, R000[|x|,x,x,x] + vabs.q R000, R000[-x,x,x,x] + vabs.q R000, R000[0,x,x,x] + vneg.q R000, R000[0,x,x,x] + vt4444.q R000, R000[-x,x,x,x] # Force some (non-delay-slot) zero bytes, to make 'objdump' print ... .align 4, 0 diff --git a/gas/testsuite/gas/mips/allegrex-vfpu.d b/gas/testsuite/gas/mips/allegrex-vfpu.d index c39541364d5..ce91768e006 100644 --- a/gas/testsuite/gas/mips/allegrex-vfpu.d +++ b/gas/testsuite/gas/mips/allegrex-vfpu.d @@ -79,4 +79,53 @@ Disassembly of section .text: 0x00000118 dc00000a vpfxs z,z,x,x 0x0000011c dd000018 vpfxt x,z,y,x 0x00000120 64228020 vmul.t R000.t,C000.t,R002.t +0x00000124 d0013f00 vabs.s S000.s,S731.s +0x00000128 d00158f8 vabs.p R620.p,C602.p +0x0000012c d001d878 vabs.t R610.t,C601.t +0x00000130 d00184a0 vabs.q R000.q,C100.q +0x00000134 d03e2480 vi2us.p S000.s,R100.p +0x00000138 d03ea0a0 vi2us.q R000.p,R000.q +0x0000013c d0023f04 vneg.s S100.s,S731.s +0x00000140 d00258e4 vneg.p R120.p,C602.p +0x00000144 d002d864 vneg.t R110.t,C601.t +0x00000148 d00284a4 vneg.q R100.q,C100.q +0x0000014c d0442b04 vocp.s S100.s,S231.s +0x00000150 d04448e4 vocp.p R120.p,C202.p +0x00000154 d044c864 vocp.t R110.t,C201.t +0x00000158 d04488a4 vocp.q R100.q,C200.q +0x0000015c d007002f vone.s S331.s +0x00000160 d00700ce vone.p C322.p +0x00000164 d007804d vone.t C311.t +0x00000168 d007808c vone.q C300.q +0x0000016c d0042f00 vsat0.s S000.s,S331.s +0x00000170 d0044ce0 vsat0.p R020.p,C302.p +0x00000174 d004cc60 vsat0.t R010.t,C301.t +0x00000178 d0048ca0 vsat0.q R000.q,C300.q +0x0000017c d0052f00 vsat1.s S000.s,S331.s +0x00000180 d0054ce0 vsat1.p R020.p,C302.p +0x00000184 d005cc60 vsat1.t R010.t,C301.t +0x00000188 d0058ca0 vsat1.q R000.q,C300.q +0x0000018c 656344f4 vscl.p R520.p,C102.p,S033.s +0x00000190 6543c474 vscl.t R510.t,C101.t,S032.s +0x00000194 652384b4 vscl.q R500.q,C100.q,S031.s +0x00000198 6eeb3f00 vscmp.s S000.s,S731.s,S233.s +0x0000019c 6ed858f8 vscmp.p R620.p,C602.p,C602.p +0x000001a0 6ed8d878 vscmp.t R610.t,C601.t,C601.t +0x000001a4 6e8484a0 vscmp.q R000.q,C100.q,C100.q +0x000001a8 d059a4a0 vt4444.q R000.p,R100.q +0x000001ac d05aa4a0 vt5551.q R000.p,R100.q +0x000001b0 d05ba4a0 vt5650.q R000.p,R100.q +0x000001b4 dc00001b vpfxs w,z,y,x +0x000001b8 d001a0a0 vabs.q R000.q,R000.q +0x000001bc dc00001b vpfxs w,z,y,x +0x000001c0 d002a0a0 vneg.q R000.q,R000.q +0x000001c4 dc00001b vpfxs w,z,y,x +0x000001c8 d059a0a0 vt4444.q R000.p,R000.q +0x000001cc dc00001b vpfxs w,z,y,x +0x000001d0 d05aa0a0 vt5551.q R000.p,R000.q +0x000001d4 dc00001b vpfxs w,z,y,x +0x000001d8 d05ba0a0 vt5650.q R000.p,R000.q +0x000001dc de000100 vpfxd m,,, +0x000001e0 dc000050 vpfxs x,x,y,y +0x000001e4 d03ea0a0 vi2us.q R000.p,R000.q \.\.\. diff --git a/gas/testsuite/gas/mips/allegrex-vfpu.s b/gas/testsuite/gas/mips/allegrex-vfpu.s index 228c17229f8..c40acb84ca9 100644 --- a/gas/testsuite/gas/mips/allegrex-vfpu.s +++ b/gas/testsuite/gas/mips/allegrex-vfpu.s @@ -71,6 +71,49 @@ vadd.q R000, C000[x,x,y,y], R002[z,z,w,w] vmul.t R000[,m,], C000[z,z,x], R002[x,z,y] + vabs.s S000, S731 + vabs.p R620, C602 + vabs.t R610, C601 + vabs.q R000, C100 + vi2us.p S000, R100 + vi2us.q R000, R000 + vneg.s S100, S731 + vneg.p R120, C602 + vneg.t R110, C601 + vneg.q R100, C100 + vocp.s S100, S231 + vocp.p R120, C202 + vocp.t R110, C201 + vocp.q R100, C200 + vone.s S331 + vone.p C322 + vone.t C311 + vone.q C300 + vsat0.s S000, S331 + vsat0.p R020, C302 + vsat0.t R010, C301 + vsat0.q R000, C300 + vsat1.s S000, S331 + vsat1.p R020, C302 + vsat1.t R010, C301 + vsat1.q R000, C300 + vscl.p R520, C102, S033 + vscl.t R510, C101, S032 + vscl.q R500, C100, S031 + vscmp.s S000, S731, S233 + vscmp.p R620, C602, C602 + vscmp.t R610, C601, C601 + vscmp.q R000, C100, C100 + vt4444.q R000.p, R100.q + vt5551.q R000.p, R100.q + vt5650.q R000.p, R100.q + vabs.q R000, R000[w,z,y,x] + vneg.q R000, R000[w,z,y,x] + vt4444.q R000, R000[w,z,y,x] + vt5551.q R000, R000[w,z,y,x] + vt5650.q R000, R000[w,z,y,x] + vi2us.q R000[m,], R000[x,x,y,y] + # Force some (non-delay-slot) zero bytes, to make 'objdump' print ... .align 4, 0 .space 16 diff --git a/include/opcode/mips.h b/include/opcode/mips.h index f535591e54d..0a8f1fd0f1c 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -252,6 +252,18 @@ enum mips_vfpu_reg_type { OP_VFPU_REG_D }; +/* Enumerates the types of VFPU register-prefix compatibility. */ +enum mips_vfpu_regpfx_compat { + /* All prefixes are allowed. */ + OP_VFPU_PFXCOMPAT_ALL, + + /* No prefixes are allowed. */ + OP_VFPU_PFXCOMPAT_NONE, + + /* Only limited (masking/swizzle) prefixes are allowed. */ + OP_VFPU_PFXCOMPAT_LIMITED +}; + /* Base class for all operands. */ struct mips_operand @@ -396,6 +408,9 @@ struct mips_vfpu_reg_operand /* Register (sub)type. */ enum mips_vfpu_reg_type regtype; + /* Register-prefix compatibility. */ + enum mips_vfpu_regpfx_compat pfxcompat; + /* Register access size. */ unsigned int rsize; }; diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index ed421e2aa71..278e09d0f76 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -1996,7 +1996,7 @@ validate_insn_args (const struct mips_opcode *opcode, if (*s == 'm' || *s == '+' || *s == '-') ++s; if (*s == '?') - s += 2; + s += 3; } } return true; @@ -2114,7 +2114,7 @@ print_insn_args (struct disassemble_info *info, if (*s == 'm' || *s == '+' || *s == '-') ++s; if (*s == '?') - s += 2; + s += 3; break; } } diff --git a/opcodes/mips-formats.h b/opcodes/mips-formats.h index d31a514d51e..00e11de1fad 100644 --- a/opcodes/mips-formats.h +++ b/opcodes/mips-formats.h @@ -112,22 +112,34 @@ return &op.root; \ } -#define VFPU_REGEXP(OP_TYPE, SIZE, LSB, REGTYPE, REGSIZE) \ +#define VFPU_REGEXP(OP, SIZE, LSB, RTYPE, RSIZE, PFXCOMPAT) \ { \ static const struct mips_vfpu_reg_operand op[] = { \ - { { OP_TYPE, SIZE, LSB }, OP_VFPU_REG_##REGTYPE, 0 }, \ - { { OP_TYPE, SIZE, LSB }, OP_VFPU_REG_##REGTYPE, 1 }, \ - { { OP_TYPE, SIZE, LSB }, OP_VFPU_REG_##REGTYPE, 2 }, \ - { { OP_TYPE, SIZE, LSB }, OP_VFPU_REG_##REGTYPE, 3 }, \ + { { OP_VFPU_##OP, SIZE, LSB }, OP_VFPU_REG_##RTYPE, PFXCOMPAT, 0 }, \ + { { OP_VFPU_##OP, SIZE, LSB }, OP_VFPU_REG_##RTYPE, PFXCOMPAT, 1 }, \ + { { OP_VFPU_##OP, SIZE, LSB }, OP_VFPU_REG_##RTYPE, PFXCOMPAT, 2 }, \ + { { OP_VFPU_##OP, SIZE, LSB }, OP_VFPU_REG_##RTYPE, PFXCOMPAT, 3 }, \ }; \ - return &op[REGSIZE].root; \ + return &op[RSIZE].root; \ } -#define VFPU_REG(SIZE, LSB, REGTYPE, REGSIZE) \ - VFPU_REGEXP(OP_VFPU_REG, SIZE, LSB, REGTYPE, REGSIZE) +#define VFPU_REG(SIZE, LSB, RTYPE, RSIZE, PFX_COMPAT) \ + { \ + switch (PFX_COMPAT) \ + { \ + case 'a': \ + VFPU_REGEXP(REG, SIZE, LSB, RTYPE, RSIZE, OP_VFPU_PFXCOMPAT_ALL) \ + case 'n': \ + VFPU_REGEXP(REG, SIZE, LSB, RTYPE, RSIZE, OP_VFPU_PFXCOMPAT_NONE) \ + case 'l': \ + VFPU_REGEXP(REG, SIZE, LSB, RTYPE, RSIZE, OP_VFPU_PFXCOMPAT_LIMITED) \ + default: \ + abort(); \ + } \ + } -#define VFPU_PFX(SIZE, LSB, REGTYPE, REGSIZE) \ - VFPU_REGEXP(OP_VFPU_PFX, SIZE, LSB, REGTYPE, REGSIZE) +#define VFPU_PFX(SIZE, LSB, RTYPE, RSIZE) \ + VFPU_REGEXP(PFX, SIZE, LSB, RTYPE, RSIZE, OP_VFPU_PFXCOMPAT_ALL) #define PCREL(SIZE, LSB, IS_SIGNED, SHIFT, ALIGN_LOG2, INCLUDE_ISA_BIT, \ FLIP_ISA_BIT) \ diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index e8c0418f1ca..b5dd46f9cf4 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -145,9 +145,9 @@ decode_mips_operand (const char *p) case '?': switch (p[1]) { - case 'd': VFPU_REG(7, 0, D, p[2] - '0'); - case 's': VFPU_REG(7, 8, S, p[2] - '0'); - case 't': VFPU_REG(7, 16, T, p[2] - '0'); + case 'd': VFPU_REG(7, 0, D, p[2] - '0', p[3]); + case 's': VFPU_REG(7, 8, S, p[2] - '0', p[3]); + case 't': VFPU_REG(7, 16, T, p[2] - '0', p[3]); case 'p': switch (p[2]) { @@ -687,63 +687,99 @@ const struct mips_opcode mips_builtin_opcodes[] = {"vnop", "", 0xffff0000, 0xffffffff, CP, 0, ALX, 0, 0 }, /* Allegrex VFPU coprocessor. Redefines coprocessor 2 and 3 (and other unused opcodes). */ -{"vadd.p", "?d1,?s1,?t1", 0x60000080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vadd.q", "?d3,?s3,?t3", 0x60008080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vadd.s", "?d0,?s0,?t0", 0x60000000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vadd.t", "?d2,?s2,?t2", 0x60008000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vavg.p", "?d0,?s1", 0xd0470080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vavg.q", "?d0,?s3", 0xd0478080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vavg.t", "?d0,?s2", 0xd0478000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vdot.p", "?d0,?s1,?t1", 0x64800080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vdot.q", "?d0,?s3,?t3", 0x64808080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vdot.t", "?d0,?s2,?t2", 0x64808000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vfad.p", "?d0,?s1", 0xd0460080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vfad.q", "?d0,?s3", 0xd0468080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vfad.t", "?d0,?s2", 0xd0468000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vabs.p", "?d1a,?s1l", 0xd0010080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vabs.q", "?d3a,?s3l", 0xd0018080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vabs.s", "?d0a,?s0l", 0xd0010000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vabs.t", "?d2a,?s2l", 0xd0018000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vadd.p", "?d1a,?s1a,?t1a", 0x60000080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vadd.q", "?d3a,?s3a,?t3a", 0x60008080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vadd.s", "?d0a,?s0a,?t0a", 0x60000000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vadd.t", "?d2a,?s2a,?t2a", 0x60008000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vavg.p", "?d0a,?s1a", 0xd0470080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vavg.q", "?d0a,?s3a", 0xd0478080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vavg.t", "?d0a,?s2a", 0xd0478000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vdot.p", "?d0a,?s1a,?t1a", 0x64800080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vdot.q", "?d0a,?s3a,?t3a", 0x64808080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vdot.t", "?d0a,?s2a,?t2a", 0x64808000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vfad.p", "?d0a,?s1a", 0xd0460080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vfad.q", "?d0a,?s3a", 0xd0468080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vfad.t", "?d0a,?s2a", 0xd0468000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, {"vflush", "", 0xffff040d, 0xffffffff, CP, 0, ALX, 0, 0 }, -{"vidt.p", "?d1", 0xd0030080, 0xffffff80, WR_C2, 0, ALX, 0, 0 }, -{"vidt.q", "?d3", 0xd0038080, 0xffffff80, WR_C2, 0, ALX, 0, 0 }, -{"vmax.p", "?d1,?s1,?t1", 0x6d800080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vmax.q", "?d3,?s3,?t3", 0x6d808080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vmax.s", "?d0,?s0,?t0", 0x6d800000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vmax.t", "?d2,?s2,?t2", 0x6d808000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vmin.p", "?d1,?s1,?t1", 0x6d000080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vmin.q", "?d3,?s3,?t3", 0x6d008080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vmin.s", "?d0,?s0,?t0", 0x6d000000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vmin.t", "?d2,?s2,?t2", 0x6d008000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vmov.p", "?d1,?s1", 0xd0000080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vmov.q", "?d3,?s3", 0xd0008080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vmov.s", "?d0,?s0", 0xd0000000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vmov.t", "?d2,?s2", 0xd0008000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vmul.p", "?d1,?s1,?t1", 0x64000080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vmul.q", "?d3,?s3,?t3", 0x64008080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vmul.s", "?d0,?s0,?t0", 0x64000000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vmul.t", "?d2,?s2,?t2", 0x64008000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vpfxd", "?pd", 0xde000000, 0xff000000, CP, ALXPFX, ALX, 0, 0 }, -{"vpfxs", "?ps", 0xdc000000, 0xff000000, CP, ALXPFX, ALX, 0, 0 }, -{"vpfxt", "?pt", 0xdd000000, 0xff000000, CP, ALXPFX, ALX, 0, 0 }, -{"vsge.p", "?d1,?s1,?t1", 0x6f000080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vsge.q", "?d3,?s3,?t3", 0x6f008080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vsge.s", "?d0,?s0,?t0", 0x6f000000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vsge.t", "?d2,?s2,?t2", 0x6f008000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vsgn.p", "?d1,?s1", 0xd04a0080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vsgn.q", "?d3,?s3", 0xd04a8080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vsgn.s", "?d0,?s0", 0xd04a0000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vsgn.t", "?d2,?s2", 0xd04a8000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vslt.p", "?d1,?s1,?t1", 0x6f800080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vslt.q", "?d3,?s3,?t3", 0x6f808080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vslt.s", "?d0,?s0,?t0", 0x6f800000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vslt.t", "?d2,?s2,?t2", 0x6f808000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vsub.p", "?d1,?s1,?t1", 0x60800080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vsub.q", "?d3,?s3,?t3", 0x60808080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vsub.s", "?d0,?s0,?t0", 0x60800000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, -{"vsub.t", "?d2,?s2,?t2", 0x60808000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vi2us.p", "?d0l,?s1l", 0xd03e0080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vi2us.q", "?d1l,?s3l", 0xd03e8080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vidt.p", "?d1a", 0xd0030080, 0xffffff80, WR_C2, 0, ALX, 0, 0 }, +{"vidt.q", "?d3a", 0xd0038080, 0xffffff80, WR_C2, 0, ALX, 0, 0 }, +{"vmax.p", "?d1a,?s1a,?t1a", 0x6d800080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vmax.q", "?d3a,?s3a,?t3a", 0x6d808080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vmax.s", "?d0a,?s0a,?t0a", 0x6d800000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vmax.t", "?d2a,?s2a,?t2a", 0x6d808000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vmin.p", "?d1a,?s1a,?t1a", 0x6d000080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vmin.q", "?d3a,?s3a,?t3a", 0x6d008080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vmin.s", "?d0a,?s0a,?t0a", 0x6d000000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vmin.t", "?d2a,?s2a,?t2a", 0x6d008000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vmov.p", "?d1a,?s1a", 0xd0000080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vmov.q", "?d3a,?s3a", 0xd0008080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vmov.s", "?d0a,?s0a", 0xd0000000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vmov.t", "?d2a,?s2a", 0xd0008000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vmul.p", "?d1a,?s1a,?t1a", 0x64000080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vmul.q", "?d3a,?s3a,?t3a", 0x64008080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vmul.s", "?d0a,?s0a,?t0a", 0x64000000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vmul.t", "?d2a,?s2a,?t2a", 0x64008000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vneg.p", "?d1a,?s1l", 0xd0020080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vneg.q", "?d3a,?s3l", 0xd0028080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vneg.s", "?d0a,?s0l", 0xd0020000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vneg.t", "?d2a,?s2l", 0xd0028000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vocp.p", "?d1a,?s1n", 0xd0440080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vocp.q", "?d3a,?s3n", 0xd0448080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vocp.s", "?d0a,?s0n", 0xd0440000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vocp.t", "?d2a,?s2n", 0xd0448000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vone.p", "?d1a", 0xd0070080, 0xffffff80, WR_C2, 0, ALX, 0, 0 }, +{"vone.q", "?d3a", 0xd0078080, 0xffffff80, WR_C2, 0, ALX, 0, 0 }, +{"vone.s", "?d0a", 0xd0070000, 0xffffff80, WR_C2, 0, ALX, 0, 0 }, +{"vone.t", "?d2a", 0xd0078000, 0xffffff80, WR_C2, 0, ALX, 0, 0 }, +{"vpfxd", "?pd.", 0xde000000, 0xff000000, CP, ALXPFX, ALX, 0, 0 }, +{"vpfxs", "?ps.", 0xdc000000, 0xff000000, CP, ALXPFX, ALX, 0, 0 }, +{"vpfxt", "?pt.", 0xdd000000, 0xff000000, CP, ALXPFX, ALX, 0, 0 }, +{"vsat0.p", "?d1n,?s1a", 0xd0040080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsat0.q", "?d3n,?s3a", 0xd0048080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsat0.s", "?d0n,?s0a", 0xd0040000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsat0.t", "?d2n,?s2a", 0xd0048000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsat1.p", "?d1n,?s1a", 0xd0050080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsat1.q", "?d3n,?s3a", 0xd0058080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsat1.s", "?d0n,?s0a", 0xd0050000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsat1.t", "?d2n,?s2a", 0xd0058000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vscl.p", "?d1a,?s1a,?t0n", 0x65000080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vscl.q", "?d3a,?s3a,?t0n", 0x65008080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vscl.t", "?d2a,?s2a,?t0n", 0x65008000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vscmp.p", "?d1a,?s1a,?t1a", 0x6e800080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vscmp.q", "?d3a,?s3a,?t3a", 0x6e808080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vscmp.s", "?d0a,?s0a,?t0a", 0x6e800000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vscmp.t", "?d2a,?s2a,?t2a", 0x6e808000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsge.p", "?d1a,?s1a,?t1a", 0x6f000080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsge.q", "?d3a,?s3a,?t3a", 0x6f008080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsge.s", "?d0a,?s0a,?t0a", 0x6f000000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsge.t", "?d2a,?s2a,?t2a", 0x6f008000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsgn.p", "?d1a,?s1a", 0xd04a0080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsgn.q", "?d3a,?s3a", 0xd04a8080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsgn.s", "?d0a,?s0a", 0xd04a0000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsgn.t", "?d2a,?s2a", 0xd04a8000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vslt.p", "?d1a,?s1a,?t1a", 0x6f800080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vslt.q", "?d3a,?s3a,?t3a", 0x6f808080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vslt.s", "?d0a,?s0a,?t0a", 0x6f800000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vslt.t", "?d2a,?s2a,?t2a", 0x6f808000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsub.p", "?d1a,?s1a,?t1a", 0x60800080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsub.q", "?d3a,?s3a,?t3a", 0x60808080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsub.s", "?d0a,?s0a,?t0a", 0x60800000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vsub.t", "?d2a,?s2a,?t2a", 0x60808000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 }, {"vsync", "", 0xffff0320, 0xffffffff, CP, 0, ALX, 0, 0 }, {"vsync", "i", 0xffff0000, 0xffff0000, CP, 0, ALX, 0, 0 }, -{"vzero.p", "?d1", 0xd0060080, 0xffffff80, WR_C2, 0, ALX, 0, 0 }, -{"vzero.q", "?d3", 0xd0068080, 0xffffff80, WR_C2, 0, ALX, 0, 0 }, -{"vzero.s", "?d0", 0xd0060000, 0xffffff80, WR_C2, 0, ALX, 0, 0 }, -{"vzero.t", "?d2", 0xd0068000, 0xffffff80, WR_C2, 0, ALX, 0, 0 }, +{"vt4444.q", "?d1n,?s3l", 0xd0598080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vt5551.q", "?d1n,?s3l", 0xd05a8080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vt5650.q", "?d1n,?s3l", 0xd05b8080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 }, +{"vzero.p", "?d1a", 0xd0060080, 0xffffff80, WR_C2, 0, ALX, 0, 0 }, +{"vzero.q", "?d3a", 0xd0068080, 0xffffff80, WR_C2, 0, ALX, 0, 0 }, +{"vzero.s", "?d0a", 0xd0060000, 0xffffff80, WR_C2, 0, ALX, 0, 0 }, +{"vzero.t", "?d2a", 0xd0068000, 0xffffff80, WR_C2, 0, ALX, 0, 0 }, {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 }, {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -- 2.51.1
