> I am trying to figure out a way not to lose the opportunity when shift > truncation is not combined in a bit test pattern. Can we keep the > explicit truncation in RTL, but generate truncation code in assembly? > Then only shift truncation which not combined in a bit test > pattershift truncationn will happen. > > (define_insn "*<shift_insn_and><mode>" > [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") > (any_shiftrt:SWI48 > (match_operand:SWI48 1 "nonimmediate_operand" "0") > (subreg:QI > (and:SI > (match_operand:SI 2 "nonimmediate_operand" "c") > (match_operand:SI 3 "const_int_operand" "n")) 0))) > (clobber (reg:CC FLAGS_REG))] > "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" > { > if ((INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1)) > == GET_MODE_BITSIZE (<MODE>mode)-1) > return "and\t{%3, %2|%2, %3}\n\r shift\t{%b2, %0|%0, %b2}"; > else > "shift\t{%2, %0|%0, %2}"; > }
Sorry, rectify a mistake: { if ((INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1)) == GET_MODE_BITSIZE (<MODE>mode)-1) return "shift\t{%2, %0|%0, %2}"; else return "and\t{%3, %2|%2, %3}\n\r shift\t{%b2, %0|%0, %b2}"; } Thanks, Wei.