On Mon, Mar 25, 2013 at 6:33 PM, Wei Mi <w...@google.com> wrote:
>> I am trying to figure out a way not to lose the opportunity when shift
>> truncation is not combined in a bit test pattern. Can we keep the
>> explicit truncation in RTL, but generate truncation code in assembly?
>> Then only shift truncation which not combined in a bit test
>> pattershift truncationn will happen.
>>
>> (define_insn "*<shift_insn_and><mode>"
>>   [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
>>         (any_shiftrt:SWI48
>>           (match_operand:SWI48 1 "nonimmediate_operand" "0")
>>           (subreg:QI
>>             (and:SI
>>               (match_operand:SI 2 "nonimmediate_operand" "c")
>>               (match_operand:SI 3 "const_int_operand" "n")) 0)))
>>    (clobber (reg:CC FLAGS_REG))]
>>   "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
>> {
>>    if ((INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
>>       == GET_MODE_BITSIZE (<MODE>mode)-1)
>>       return "and\t{%3, %2|%2, %3}\n\r shift\t{%b2, %0|%0, %b2}";
>>    else
>>       "shift\t{%2, %0|%0, %2}";
>> }
>
> Sorry, rectify a mistake:
>
> {
>    if ((INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
>       == GET_MODE_BITSIZE (<MODE>mode)-1)
>       return "shift\t{%2, %0|%0, %2}";
>    else
>       return "and\t{%3, %2|%2, %3}\n\r shift\t{%b2, %0|%0, %b2}";
> }

I'm not sure the existing patterns are wrong because SHIFT_COUNT_TRUNCATED
is false for x86 AFAIK, exactly because of the bit-test vs. shift instruction
differences.  So there is no inconsistency.  The i386 backend seems to
try to follow my suggestion as if SHIFT_COUNT_TRUNCATED didn't exist
(well, it's false, so it technically doesn't exist for i386) and recognizes
the shift with truncate with the *<shift_insn><mode>3_mask splitter.
But I'm not sure why it bothers to do it with a splitter instead of just
with a define_insn?  Because the split code,

  [(parallel [(set (match_dup 0)
                   (any_shiftrt:SWI48 (match_dup 1) (match_dup 2)))
              (clobber (reg:CC FLAGS_REG))])]

is wrong and could be combined into a bit-test instruction.  No?

That is, why not have define_insn variants for shift instructions with
explicit truncation?

Richard.


> Thanks,
> Wei.

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