This patch documents the previously undocumented -mupper-regs-df and
-mupper-regs-sf switches. It also provides feature test macros that users can
use to determine if the upper register support is enabled.
Once the prevous patches have gone in, is this patch ok to install?
2014-11-11 Michael Meissner <meiss...@linux.vnet.ibm.com>
* config/rs6000/rs6000.opt (-mupper-regs-df): Make option public.
(-mupper-regs-sf): Likewise.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
__UPPER_REGS_DF__ if -mupper-regs-df. Define __UPPER_REGS_SF__ if
-mupper-regs-sf.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mupper-regs-{sf,df}.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.opt
===================================================================
--- gcc/config/rs6000/rs6000.opt (revision 217376)
+++ gcc/config/rs6000/rs6000.opt (working copy)
@@ -582,12 +582,12 @@ Target Report Var(rs6000_compat_align_pa
Generate aggregate parameter passing code with at most 64-bit alignment.
mupper-regs-df
-Target Undocumented Mask(UPPER_REGS_DF) Var(rs6000_isa_flags)
+Target Report Mask(UPPER_REGS_DF) Var(rs6000_isa_flags)
Allow double variables in upper registers with -mcpu=power7 or -mvsx
mupper-regs-sf
-Target Undocumented Mask(UPPER_REGS_SF) Var(rs6000_isa_flags)
-Allow float variables in upper registers with -mcpu=power8 or -mp8-vector
+Target Report Mask(UPPER_REGS_SF) Var(rs6000_isa_flags)
+Allow float variables in upper registers with -mcpu=power8 or -mpower8-vector
moptimize-swaps
Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
Index: gcc/config/rs6000/rs6000-c.c
===================================================================
--- gcc/config/rs6000/rs6000-c.c (revision 217376)
+++ gcc/config/rs6000/rs6000-c.c (working copy)
@@ -380,6 +380,10 @@ rs6000_target_modify_macros (bool define
rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__");
if ((flags & OPTION_MASK_CRYPTO) != 0)
rs6000_define_or_undefine_macro (define_p, "__CRYPTO__");
+ if ((flags & OPTION_MASK_UPPER_REGS_DF) != 0)
+ rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_DF__");
+ if ((flags & OPTION_MASK_UPPER_REGS_SF) != 0)
+ rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_SF__");
/* options from the builtin masks. */
if ((bu_mask & RS6000_BTM_SPE) != 0)
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi (revision 217376)
+++ gcc/doc/invoke.texi (working copy)
@@ -939,7 +939,8 @@ See RS/6000 and PowerPC Options.
-mcrypto -mno-crypto -mdirect-move -mno-direct-move @gol
-mquad-memory -mno-quad-memory @gol
-mquad-memory-atomic -mno-quad-memory-atomic @gol
--mcompat-align-parm -mno-compat-align-parm}
+-mcompat-align-parm -mno-compat-align-parm @gol
+-mupper-regs-df -mno-upper-regs-df -mupper-regs-sf -mno-upper-regs-sf}
@emph{RX Options}
@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol
@@ -19685,6 +19686,30 @@ Generate code that uses (does not use) t
instructions. The @option{-mquad-memory-atomic} option requires use of
64-bit mode.
+@item -mupper-regs-df
+@itemx -mno-upper-regs-df
+@opindex mupper-regs-df
+@opindex mno-upper-regs-df
+Generate code that uses (does not use) the scalar double precision
+instructions that target all 64 registers in the vector/scalar
+floating point register set that were added in version 2.06 of the
+PowerPC ISA. If @option{-mupper-regs-df} is not set, the traditional
+floating instructions will be generated that target the first 32
+registers. This option requires the @option{-mvsx},
+@option{-mcpu=power7}, or @option{-mcpu=power8} options to be set.
+
+@item -mupper-regs-sf
+@itemx -mno-upper-regs-sf
+@opindex mupper-regs-sf
+@opindex mno-upper-regs-sf
+Generate code that uses (does not use) the scalar single precision
+instructions that target all 64 registers in the vector/scalar
+floating point register set that were added in version 2.07 of the
+PowerPC ISA. If @option{-mupper-regs-sf} is not set, the traditional
+floating instructions will be generated that target the first 32
+registers. This option requires the @option{-mpower8-vector},
+@option{-mcpu=power7}, or @option{-mcpu=power8} options to be set.
+
@item -mfloat-gprs=@var{yes/single/double/no}
@itemx -mfloat-gprs
@opindex mfloat-gprs
