This patch fixes the failures in the following tests if --with-cpu is not used to set the cpu to cpus with vsx enabled (power7/power8):
gcc.target/powerpc/altivec-splat.c gcc.target/powerpc/pr27158.c I have built these patches on power7 systems (default cpu = power7, and power6), power8 systems (default cpu = power8 and power5). The compilers bootstrap and do not have regressions. Are the patches ok to install? 2014-11-20 Michael Meissner <meiss...@linux.vnet.ibm.com> PR target/63965 * config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Do not set Altivec & -16 mask if the type is not valid for Altivec registers. (rs6000_secondary_reload_memory): Add support for ((reg + const) + reg) that occurs during push_reload processing. * config/rs6000/altivec.md (altivec_mov<mode>): Add instruction alternative for moving constant vectors which are easy altivec constants to GPRs. Set the length attribute each of the alternatives. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 217802) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -2505,7 +2505,8 @@ rs6000_setup_reg_addr_masks (void) /* VMX registers can do (REG & -16) and ((REG+REG) & -16) addressing on 128-bit types. */ - if (rc == RELOAD_REG_VMX && GET_MODE_SIZE (m2) == 16) + if (rc == RELOAD_REG_VMX && GET_MODE_SIZE (m2) == 16 + && (addr_mask & RELOAD_REG_VALID) != 0) addr_mask |= RELOAD_REG_AND_M16; reg_addr[m].addr_mask[rc] = addr_mask; @@ -16652,6 +16653,17 @@ rs6000_secondary_reload_memory (rtx addr } } + /* (plus (plus (reg) (constant)) (reg)) is also generated during + push_reload processing, so handle it now. */ + else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1)) + { + if ((addr_mask & RELOAD_REG_INDEXED) == 0) + { + extra_cost = 1; + type = "indexed #2"; + } + } + else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0))) { fail_msg = "no base register #2"; Index: gcc/config/rs6000/altivec.md =================================================================== --- gcc/config/rs6000/altivec.md (revision 217802) +++ gcc/config/rs6000/altivec.md (working copy) @@ -189,8 +189,8 @@ (define_mode_attr VU_char [(V2DI "w") (V ;; Vector move instructions. (define_insn "*altivec_mov<mode>" - [(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*Y,*r,*r,v,v") - (match_operand:VM2 1 "input_operand" "v,Z,v,r,Y,r,j,W"))] + [(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*Y,*r,*r,v,v,*r") + (match_operand:VM2 1 "input_operand" "v,Z,v,r,Y,r,j,W,W"))] "VECTOR_MEM_ALTIVEC_P (<MODE>mode) && (register_operand (operands[0], <MODE>mode) || register_operand (operands[1], <MODE>mode))" @@ -205,10 +205,12 @@ (define_insn "*altivec_mov<mode>" case 5: return "#"; case 6: return "vxor %0,%0,%0"; case 7: return output_vec_const_move (operands); + case 8: return "#"; default: gcc_unreachable (); } } - [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*")]) + [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*,*") + (set_attr "length" "4,4,4,20,20,20,4,8,32")]) ;; Unlike other altivec moves, allow the GPRs, since a normal use of TImode ;; is for unions. However for plain data movement, slightly favor the vector