----- Forwarded message from Richard Braun <[email protected]> -----
Date: Thu, 6 Nov 2025 10:21:16 +0100
From: Richard Braun <[email protected]>
To: Benoit Dinechin <[email protected]>
Subject: Re: Question about conditional functional unit reservation
On Thu, Nov 06, 2025 at 07:55:53AM +0000, Benoit Dinechin wrote:
> Did you try adjusting the latencies with a (define_bypass ...)? For our KVX
> VLIW cores, we have for instance:
>
> ;; The integer MAC accumulator reads its input cycle later than other
> execution units.
> (define_bypass 1 "kv*_mul*_int*,kv*_madd_int*"
> "kv*_madd_int*"
> "kvx_accumulator_bypass_p")
>
> Then the trigger for the bypass is defined as:
>
> int
> kvx_accumulator_bypass_p (rtx_insn *prod_insn, rtx_insn *cons_insn)
>
> {
> rtx prod_set = single_set (prod_insn);
> if (!prod_set)
> return 0;
>
> rtx cons_set = single_set (cons_insn);
>
> if (!cons_set)
> return 0;
>
> rtx produced = SET_DEST (prod_set);
> // KVX ternary insns use the same register for acccumulator and result.
> rtx consumed = SET_DEST (cons_set);
>
> // Depends on renaming constraint so only works in SCHED2.
> return reg_overlap_mentioned_p (produced, consumed);
>
> }
That's a good idea indeed.
I'll try it and report, thanks.
Any reason why you didn't Cc'd the GCC mailing list though ?
--
Richard Braun
----- End forwarded message -----
--
Richard Braun
