Hi! I am new to backend development and am trying to get my head around how to implement a custom CPU backend. I have read a lot around the area but am still left with a lot of gaps in my knowledge.
I have a very basic machine description with just addsi3, subsi3, movsi and basic jump and rts. I can compile some very simple functions with cc1 to asm, so I’m happy with the start. One question on the instruction definitions I have in general is, do all variants need to be in the one definition? I see from things like mov_optab that it only seems to be one definition per machine mode? I have included valid r2r, i2r, r2m, etc. instructions in movsi and that works, but these are just basic forms. I have other load and store forms, but I’m not sure how or when these are selected and it doesn’t seem easy or appropriate to encode in the one definition (different numbers of parameters). For example I have an immediate offset indexed store and load instructions, but cc1 emits a series of adds from the frame pointer to initialise temp registers to store the passed variables into the frame and then reload. The immediate indexed store would fit this perfectly but for whatever reason this pattern is not matched. What is the correct way to coerce the selection of the preferred indexed load or store here? Similarly I have the basic patterns for rrr / irr for addsi3 / subsi3 but have more specific patterns for instruction embedded quick data, short immediate, etc, how do these get selected? Any clarification on the whole pattern selection process would be fantastic. I’m starting to get a minor grip on things. Thanks! — James
