On 18/03/2026 14:28, Richard Biener wrote:
OK, so MEMs with vectors would be "special" then. IIRC atomics are UNSPECs(?)
Atomic read and write need to be UNSPECs otherwise they'd look exactly like regular reads and write and recog would pick the wrong one. Compare and swap not-so-much, but there's not really an RTX code for that, so UNSPEC it is (well, UNSPECV, probably).
Also, you usually want somewhere to keep the memory model that controls the cache behaviour, if that's an issue on your architecture.
Andrew
