Matt Lee wrote:
Hi,
I am working with GCC-4.1.1 on a simple 5-pipe stage simple scalar
RISC processors with the following description for loads and stores,
(define_insn_reservation "integer" 1
(eq_attr "type" "branch,jump,call,arith,darith,icmp,nop")
"issue,iu,wb")
(define_insn_reservation "load" 3
(eq_attr "type" "load")
"issue,iu,wb")
(define_insn_reservation "store" 1
(eq_attr "type" "store")
"issue,iu,wb")
I am seeing poor scheduling in Dhrystone where a memcpy call is
expanded inline.
memcpy (&dst, &src, 16) ==>
load 1, rA + 4
store 1, rB + 4
load 2, rA + 8
store 2, rB + 8
...
I agree with Adam, that this is most probably an aliasing issue. Take a
look at the dependency map (you can get it with -fsched-verbose=6 flag
in your command line).
--
Maxim
