support single predicate set instructions in GCC-4.1.1

[吴曦]

Hi.

I am working on Itanium architecture and GCC-4.1.1.

I modify the machine description file ia64.md to support single
predicate set  instruction such as:

     (%0) cmp.ne %1, p0 = %2, %3

here %0 and %1 are predicates, %2 is a register or immediate, %3 is a
register operand.

more specifically, I add the following define_insn:

(define_insn "*shift_predicate_cmp"
  [(set (const_int 0)
    (and:BI (and:BI (match_operand:BI 1 "register_operand" "c")
            (and:BI (match_operand:DI 2 "gr_reg_or_8bit_adjusted_operand" "rL")
                       (match_operand:DI 3 "gr_register_operand" "r")))
        (match_operand:BI 0 "register_operand" "c")))]
  ""
  "(%0) cmp.ne %1, p0 = %2, %3"
  [(set_attr "itanium_class" "icmp")])

I make this define_insn anonymous because I only need this type of
instruction sometimes, and I can generate this pattern manually; the
generation function is:

rtx gen_shift_predicate_cmp (rtx op0, rtx op1, rtx op2, rtx op3)
{
  return gen_rtx_SET(BImode, CONST0_RTX(BImode),
                     gen_rtx_AND(BImode, gen_rtx_AND(BImode, op1,

gen_rtx_AND(BImode, op2, op3)),
                                 op0));
}

After adding these support, I recompile gcc and insert some
instructions of this kind into insn list, the generation and matching
works fine. BUT, the generation of insn group barrier (';;' on Itanium
architecture) doesn't work fine, and it generates code like:

    .loc 1 118 0
    (p0) cmp.ne p15, p0 = 0, r30
    .loc 1 121 0
    (p0) cmp.ne p15, p0 = 0, r30

it warns "WAW" and there should be stop ";;" between these two
instructions. Intuitively, I think I should modify some part of GCC to
generate correct ";;" as there is a new type of define_insn. But I
don't know where exactly to do this modification to correct the error
:-(, any help ?

Any help is truely appreciated !

Thanks very much