Dear GCC Developers/Users, I am working on a port of a target backend to PISA architecture (a MIPS-IV like ISA used by the SimpleScalar simulator). When compiling libgcc2 for __muldi3:
#ifdef L_muldi3 DWtype __muldi3 (DWtype u, DWtype v) { const DWunion uu = {.ll = u}; const DWunion vv = {.ll = v}; DWunion w = {.ll = __umulsidi3 (uu.s.low, vv.s.low)}; w.s.high += ((UWtype) uu.s.low * (UWtype) vv.s.high + (UWtype) uu.s.high * (UWtype) vv.s.low); return w.ll; } #endif I get the following error: ../.././gcc/libgcc2.c: In function ‘__muldi3’: ../.././gcc/libgcc2.c:542: error: unable to find a register to spill in class ‘MD_REGS’ ../.././gcc/libgcc2.c:542: error: este es el insn: (insn 37 36 38 2 (set (reg:DI 116) (mult:DI (zero_extend:DI (reg:SI 3 v1 [orig:117 __ul ] [117])) (zero_extend:DI (reg:SI 2 v0 [orig:118 __vl ] [118])))) 14 {umulsidi3_32bit_internal} (nil) (expr_list:REG_DEAD (reg:SI 3 v1 [orig:117 __ul ] [117]) (expr_list:REG_DEAD (reg:SI 2 v0 [orig:118 __vl ] [118]) (nil)))) I have compile it with -da and the dumps are: greg: Spilling for insn 37. Using reg 4 for reload 0 reload failure for reload 1 Reloads for insn # 37 Reload 0: GR_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0), can't combine, secondary_reload_p Reload 1: reload_out (DI) = (reg:DI 116) MD_REGS, RELOAD_FOR_OUTPUT (opnum = 0) reload_out_reg: (reg:DI 116) secondary_out_reload = 0 lreg: [...] Register 116 costs: LEA_REGS:10000000 GR_REGS:10000000 MEM:8000 [...] Register 116 used 2 times across 2 insns in block 2; set 1 time; 8 bytes; NO_REGS or none. [...] (insn 37 36 38 2 (set (reg:DI 116) (mult:DI (zero_extend:DI (reg:SI 117 [ __ul ])) (zero_extend:DI (reg:SI 118 [ __vl ])))) 14 {umulsidi3_32bit_internal} (nil) (expr_list:REG_DEAD (reg:SI 117 [ __ul ]) (expr_list:REG_DEAD (reg:SI 118 [ __vl ]) (nil)))) [...] I have read a thread of a guy having a paroblem like this but it has not helped me. If anybody would tell me where the problem could be, I would be very pleased. Regards, Rodrigo González