nice, i'd like to put my patches on gcc-3.4.6 here for who are
interested with it. though there may be some mistakes. :-)
ericfisher
diff -up -N gcc-3.4.6/gcc/config/mips/loongson2.md
loongson-gcc-3.4.6/gcc/config/mips/loongson2.md
--- gcc-3.4.6/gcc/config/mips/loongson2.md 1970-01-01 08:00:00.000000000
+0800
+++ loongson-gcc-3.4.6/gcc/config/mips/loongson2.md 2008-04-21
23:49:22.000000000 +0800
@@ -0,0 +1,167 @@
+;; loongson2e/2f has
+;; two fix point units: alu1 and alu2,
+;; two float units: falu1 and falu2,
+;; and one memory access unit: memory
+
+(define_automaton "loongson2_int, loongson2_fp")
+
+(define_cpu_unit "alu1, alu2" "loongson2_int")
+(define_cpu_unit "mem" "loongson2_int")
+(define_cpu_unit "falu1, falu2" "loongson2_fp")
+
+;; Add/sub/logical/shift/lui/cmp
+;; MF/MT HI/LO
+;; move? condmove? li?
+(define_insn_reservation "loongson2_arith" 2
+ (and (eq_attr "cpu" "loongson2e, loongson2f")
+ (eq_attr "type" "arith, darith, hilo, move, condmove, const, icmp"))
+ "alu1|alu2")
+
+;; Trap/branch
+(define_insn_reservation "loongson2_branch" 2
+ (and (eq_attr "cpu" "loongson2e, loongson2f")
+ (eq_attr "type" "branch, jump, call"))
+ "alu1")
+
+;; (D)MULT(U)
+(define_insn_reservation "loongson2_mult" 5
+ (and (eq_attr "cpu" "loongson2e, loongson2f")
+ (eq_attr "type" "imul"))
+ "alu2*2")
+
+;; (D)MULT(U)G
+(define_insn_reservation "loongson2_multg" 5
+ (and (eq_attr "cpu" "loongson2e, loongson2f")
+ (eq_attr "type" "multg"))
+ "alu2")
+
+;; (D)DIV(U)
+;; (D)DIV(U)G
+;; (D)MOD(U)G
+(define_insn_reservation "loongson2e_div" 37
+ (and (eq_attr "cpu" "loongson2e")
+ (eq_attr "type" "idiv, divg"))
+ "alu2*37")
+
+;; (D)DIV(U)
+(define_insn_reservation "loongson2f_div" 38
+ (and (eq_attr "cpu" "loongson2f")
+ (eq_attr "type" "idiv"))
+ "alu2*76")
+
+;; (D)DIV(U)G
+;; (D)MOD(U)G
+(define_insn_reservation "loongson2f_divg" 38
+ (and (eq_attr "cpu" "loongson2f")
+ (eq_attr "type" "divg"))
+ "alu2*37")
+
+;; Load
+;; fp: Lwc1, Ldc1
+(define_insn_reservation "loongson2_load" 5
+ (and (eq_attr "cpu" "loongson2e, loongson2f")
+ (eq_attr "type" "load"))
+ "mem")
+
+;; Store?
+(define_insn_reservation "loongson2_store" 1
+ (and (eq_attr "cpu" "loongson2e, loongson2f")
+ (eq_attr "type" "store"))
+ "mem")
+
+;; (D)MTC1/(D)MFC1
+(define_insn_reservation "loongson2_c1" 5
+ (and (eq_attr "cpu" "loongson2e, loongson2f")
+ (eq_attr "type" "xfer"))
+ "mem")
+
+;; fp: Abs/Neg/C.cond/Bc1t/Bc1f/Move/Cvt*
+(define_insn_reservation "loongson2_fabs" 3
+ (and (eq_attr "cpu" "loongson2e, loongson2f")
+ (eq_attr "type" "fabs, fneg, fcmp"))
+ "falu1")
+
+;; fp: Add/Sub/Round/Trunc/Ceil/Floor/Cvt*
+(define_insn_reservation "loongson2e_fadd" 5
+ (and (eq_attr "cpu" "loongson2e")
+ (eq_attr "type" "fadd, fcvt"))
+ "falu1")
+
+;; fp: Round/Trunc/Ceil/Floor/CVT*
+(define_insn_reservation "loongson2f_fcvt" 5
+ (and (eq_attr "cpu" "loongson2f")
+ (eq_attr "type" "fcvt"))
+ "falu1")
+
+;; fp: ADD/SUB/MUL/MADD/MSUB/NMADD/NMSUB
+(define_insn_reservation "loongson2f_fadd" 7
+ (and (eq_attr "cpu" "loongson2f")
+ (eq_attr "type" "fadd, fmul, fmadd"))
+ "falu1|falu2")
+
+;; fp: Mul
+(define_insn_reservation "loongson2e_fmul" 6
+ (and (eq_attr "cpu" "loongson2e")
+ (eq_attr "type" "fmul"))
+ "falu1|falu2")
+
+;; fp: Div.s
+(define_insn_reservation "loongson2e_fdivs" 10
+ (and (eq_attr "cpu" "loongson2e")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "SF")))
+ "falu2*10")
+
+;; fp: Div.s
+(define_insn_reservation "loongson2f_fdivs" 11
+ (and (eq_attr "cpu" "loongson2f")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "SF")))
+ "falu2*10")
+
+;; fp: Div.d
+(define_insn_reservation "loongson2e_fdivd" 17
+ (and (eq_attr "cpu" "loongson2e")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "DF")))
+ "falu2*17")
+
+;; fp: Div.d
+(define_insn_reservation "loongson2f_fdivd" 18
+ (and (eq_attr "cpu" "loongson2f")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "DF")))
+ "falu2*17")
+
+;; fp: Sqrt.s
+(define_insn_reservation "loongson2e_sqrts" 16
+ (and (eq_attr "cpu" "loongson2e")
+ (and (eq_attr "type" "fsqrt")
+ (eq_attr "mode" "SF")))
+ "falu2*16")
+
+;; fp: Sqrt.s
+(define_insn_reservation "loongson2f_sqrts" 17
+ (and (eq_attr "cpu" "loongson2f")
+ (and (eq_attr "type" "fsqrt")
+ (eq_attr "mode" "SF")))
+ "falu2*16")
+
+;; fp: Sqrt.d
+(define_insn_reservation "loongson2e_sqrtd" 31
+ (and (eq_attr "cpu" "loongson2e")
+ (and (eq_attr "type" "fsqrt")
+ (eq_attr "mode" "DF")))
+ "falu2*31")
+
+;; fp: Sqrt.d
+(define_insn_reservation "loongson2f_sqrtd" 32
+ (and (eq_attr "cpu" "loongson2f")
+ (and (eq_attr "type" "fsqrt")
+ (eq_attr "mode" "DF")))
+ "falu2*31")
+
+;; for debug
+;; (automata_option "v")
+;; (automata_option "progress")
+
diff -up -N gcc-3.4.6/gcc/config/mips/mips-protos.h
loongson-gcc-3.4.6/gcc/config/mips/mips-protos.h
--- gcc-3.4.6/gcc/config/mips/mips-protos.h 2005-07-31 16:35:15.000000000
+0800
+++ loongson-gcc-3.4.6/gcc/config/mips/mips-protos.h 2008-04-21
14:20:54.000000000 +0800
@@ -146,6 +146,7 @@ extern const char *mips_output_load_labe
extern const char *mips_output_conditional_branch (rtx, rtx *, int, int,
int, int);
extern const char *mips_output_division (const char *, rtx *);
+extern const char *mips_output_division_p (const char *, rtx *);
extern unsigned int mips_hard_regno_nregs (int, enum machine_mode);
extern int mips_return_in_memory (tree);
extern const char *mips_emit_prefetch (rtx *);
diff -up -N gcc-3.4.6/gcc/config/mips/mips.c
loongson-gcc-3.4.6/gcc/config/mips/mips.c
--- gcc-3.4.6/gcc/config/mips/mips.c 2005-07-31 16:35:15.000000000 +0800
+++ loongson-gcc-3.4.6/gcc/config/mips/mips.c 2008-04-21
14:13:45.000000000 +0800
@@ -489,10 +489,10 @@ int mips_isa;
int mips_abi;
/* Strings to hold which cpu and instruction set architecture to use. */
-const char *mips_arch_string; /* for -march=<xxx> */
-const char *mips_tune_string; /* for -mtune=<xxx> */
-const char *mips_isa_string; /* for -mips{1,2,3,4} */
-const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
+const char *mips_arch_string; /* for -march=<xxx> */
+const char *mips_tune_string; /* for -mtune=<xxx> */
+const char *mips_isa_string; /* for -mips{1,2,3,4} */
+const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
/* Whether we are generating mips16 hard float code. In mips16 mode
we always set TARGET_SOFT_FLOAT; this variable is nonzero if
@@ -726,6 +726,10 @@ const struct mips_cpu_info mips_cpu_info
{ "sb1", PROCESSOR_SB1, 64 },
{ "sr71000", PROCESSOR_SR71000, 64 },
+ /* ST Microelectronics Loongson 2E and 2F cores */
+ { "loongson2e", PROCESSOR_LOONGSON2E, 3},
+ { "loongson2f", PROCESSOR_LOONGSON2F, 3},
+
/* End marker */
{ 0, 0, 0 }
};
@@ -4624,9 +4628,9 @@ override_options (void)
There's no harm in specifying both as long as the ISA levels
are the same. */
if (mips_arch_info != 0 && mips_isa != isa_info->isa)
- error ("-mips%s conflicts with the other architecture options, "
- "which specify a MIPS%d processor",
- mips_isa_string, mips_isa);
+ error ("-mips%s conflicts with the other architecture options, "
+ "which specify a MIPS%d processor",
+ mips_isa_string, mips_isa);
/* Set architecture based on the given option. */
mips_set_architecture (isa_info);
@@ -9249,6 +9253,21 @@ mips_output_division (const char *divisi
}
return division;
}
+
+/* Used to output (d)div(u).g or (d)mod(u).g instruction of loongson,
+ which takes three operands, and put the result in the rd register.
+ Hence emit the divide-by-zeor check before the DIVISION, in case
+ that the rd and rt are the same one. */
+const char *
+mips_output_division_g (const char *division, rtx *operands)
+{
+ if (TARGET_CHECK_ZERO_DIV)
+ {
+ output_asm_insn ("bne\t%2,%.,1f%#\n\tbreak\t7\n1:", operands);
+ }
+ return division;
+}
+
/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
with a final "000" replaced by "k". Ignore case.
@@ -9411,6 +9430,9 @@ mips_issue_rate (void)
case PROCESSOR_R7000:
case PROCESSOR_R9000:
return 2;
+ case PROCESSOR_LOONGSON2E:
+ case PROCESSOR_LOONGSON2F:
+ return 4;
default:
return 1;
@@ -9433,6 +9455,8 @@ mips_use_dfa_pipeline_interface (void)
case PROCESSOR_R7000:
case PROCESSOR_R9000:
case PROCESSOR_SR71000:
+ case PROCESSOR_LOONGSON2E:
+ case PROCESSOR_LOONGSON2F:
return true;
default:
@@ -9662,4 +9686,10 @@ irix_section_type_flags (tree decl, cons
#endif /* TARGET_IRIX */
+static int
+debug_insn_id(rtx insn)
+{
+ return INSN_UID(insn);
+}
+
#include "gt-mips.h"
diff -up -N gcc-3.4.6/gcc/config/mips/mips.h
loongson-gcc-3.4.6/gcc/config/mips/mips.h
--- gcc-3.4.6/gcc/config/mips/mips.h 2004-07-15 08:42:49.000000000 +0800
+++ loongson-gcc-3.4.6/gcc/config/mips/mips.h 2008-04-21
20:31:57.000000000 +0800
@@ -67,7 +67,9 @@ enum processor_type {
PROCESSOR_R8000,
PROCESSOR_R9000,
PROCESSOR_SB1,
- PROCESSOR_SR71000
+ PROCESSOR_SR71000,
+ PROCESSOR_LOONGSON2E,
+ PROCESSOR_LOONGSON2F
};
/* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
@@ -333,6 +335,8 @@ extern const struct mips_cpu_info *mips_
#define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
#define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
+#define TARGET_LOONGSON2E (mips_arch == PROCESSOR_LOONGSON2E)
+#define TARGET_LOONGSON2F (mips_arch == PROCESSOR_LOONGSON2F)
/* Scheduling target defines. */
#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
@@ -346,6 +350,8 @@ extern const struct mips_cpu_info *mips_
#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
#define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
+#define TUNE_LOONGSON2E (mips_tune == PROCESSOR_LOONGSON2E)
+#define TUNE_LOONGSON2F (mips_tune == PROCESSOR_LOONGSON2F)
#define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
@@ -773,7 +779,7 @@ extern const struct mips_cpu_info *mips_
#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
&& !TARGET_SR71K \
- && !TARGET_MIPS16)
+ && !TARGET_MIPS16)
/* Generate three-operand multiply instructions for SImode. */
#define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
@@ -783,11 +789,15 @@ extern const struct mips_cpu_info *mips_
|| TARGET_MIPS9000 \
|| ISA_MIPS32
\
|| ISA_MIPS32R2 \
- || ISA_MIPS64) \
+ || ISA_MIPS64
\
+ || TARGET_LOONGSON2E \
+ || TARGET_LOONGSON2F) \
&& !TARGET_MIPS16)
/* Generate three-operand multiply instructions for DImode. */
-#define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
+#define GENERATE_MULT3_DI ((TARGET_MIPS3900 \
+ || TARGET_LOONGSON2E \
+ || TARGET_LOONGSON2F) \
&& !TARGET_MIPS16)
/* Macros to decide whether certain features are available or not,
@@ -824,7 +834,9 @@ extern const struct mips_cpu_info *mips_
#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
- || ISA_MIPS64) \
+ || ISA_MIPS64 \
+ || TARGET_LOONGSON2E \
+ || TARGET_LOONGSON2F) \
&& !TARGET_MIPS5500 \
&& !TARGET_MIPS16)
diff -up -N gcc-3.4.6/gcc/config/mips/mips.md
loongson-gcc-3.4.6/gcc/config/mips/mips.md
--- gcc-3.4.6/gcc/config/mips/mips.md 2005-07-31 16:35:15.000000000 +0800
+++ loongson-gcc-3.4.6/gcc/config/mips/mips.md 2008-04-22
00:31:53.000000000 +0800
@@ -119,8 +119,11 @@
;; frsqrt floating point reciprocal square root
;; multi multiword sequence (or user asm statements)
;; nop no operation
+;; multg loongson (d)mult(u).g
+;; divg loongson (d)div(u).g, (d)mod(u).g
+
(define_attr "type"
-
"unknown,branch,jump,call,load,store,prefetch,prefetchx,move,condmove,xfer,hilo,const,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
+
"unknown,branch,jump,call,load,store,prefetch,prefetchx,move,condmove,xfer,hilo,const,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop,multg,divg"
(cond [(eq_attr "jal" "!unset") (const_string "call")
(eq_attr "got" "load") (const_string "load")]
(const_string "unknown")))
@@ -214,7 +217,7 @@
;; Attribute describing the processor. This attribute must match exactly
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
-
"default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
+
"default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000,loongson2e,loongson2f"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
@@ -614,6 +617,8 @@
(include "7000.md")
(include "9000.md")
(include "sr71k.md")
+(include "loongson2.md")
+
;;
;; ....................
@@ -1423,7 +1428,6 @@
(set_attr "mode" "SF")
(set_attr "length" "8")])
-
;; ??? The R4000 (only) has a cpu bug. If a double-word shift executes while
;; a multiply is in progress, it may give an incorrect result. Avoid
;; this by keeping the mflo with the mult on the R4000.
@@ -1434,7 +1438,9 @@
(match_operand:SI 2 "register_operand" "")))]
""
{
- if (GENERATE_MULT3_SI || TARGET_MAD)
+ if (TARGET_LOONGSON2E || TARGET_LOONGSON2F)
+ emit_insn (gen_mulsi3_multg (operands[0], operands[1], operands[2]));
+ else if (GENERATE_MULT3_SI || TARGET_MAD)
emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
else if (!TARGET_MIPS4000 || TARGET_MIPS16)
emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
@@ -1443,14 +1449,25 @@
DONE;
})
+(define_insn "mulsi3_multg"
+ [(set (match_operand:SI 0 "register_operand" "=d,l")
+ (mult:SI (match_operand:SI 1 "register_operand" "d,d")
+ (match_operand:SI 2 "register_operand" "d,d")))]
+ "TARGET_LOONGSON2E || TARGET_LOONGSON2F"
+{
+ return "mult.g\t%0,%1,%2";
+}
+ [(set_attr "type" "multg")
+ (set_attr "mode" "SI")])
+
(define_insn "mulsi3_mult3"
[(set (match_operand:SI 0 "register_operand" "=d,l")
(mult:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "register_operand" "d,d")))
(clobber (match_scratch:SI 3 "=h,h"))
(clobber (match_scratch:SI 4 "=l,X"))]
- "GENERATE_MULT3_SI
- || TARGET_MAD"
+ "(GENERATE_MULT3_SI
+ || TARGET_MAD) && !(TARGET_LOONGSON2E || TARGET_LOONGSON2F)"
{
if (which_alternative == 1)
return "mult\t%1,%2";
@@ -2358,6 +2375,89 @@
"nmsub.s\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
+
+;; Loongson 3-operand floating point multiply accumulate instructions.
+
+(define_insn ""
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
+ (match_operand:DF 2 "register_operand" "f"))
+ (match_dup 0)))]
+ "(TARGET_LOONGSON2E || TARGET_LOONGSON2F) && TARGET_HARD_FLOAT &&
TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
+ "madd.d\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "DF")])
+
+(define_insn ""
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
+ (match_operand:SF 2 "register_operand" "f"))
+ (match_dup 0)))]
+ "(TARGET_LOONGSON2E || TARGET_LOONGSON2F) && TARGET_HARD_FLOAT &&
TARGET_FUSED_MADD"
+ "madd.s\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "SF")])
+
+(define_insn ""
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
+ (match_operand:DF 2 "register_operand" "f"))
+ (match_dup 0)))]
+ "(TARGET_LOONGSON2E || TARGET_LOONGSON2F) && TARGET_HARD_FLOAT &&
TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
+ "msub.d\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "DF")])
+
+(define_insn ""
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
+ (match_operand:SF 2 "register_operand" "f"))
+ (match_dup 0)))]
+ "(TARGET_LOONGSON2E || TARGET_LOONGSON2F) && TARGET_HARD_FLOAT &&
TARGET_FUSED_MADD"
+ "msub.s\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "SF")])
+
+(define_insn ""
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
+ (match_operand:DF 2 "register_operand" "f"))
+ (match_dup 0))))]
+ "(TARGET_LOONGSON2E || TARGET_LOONGSON2F) && TARGET_HARD_FLOAT &&
TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
+ "nmadd.d\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "DF")])
+
+(define_insn ""
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
+ (match_operand:SF 2 "register_operand" "f"))
+ (match_dup 0))))]
+ "(TARGET_LOONGSON2E || TARGET_LOONGSON2F) && TARGET_HARD_FLOAT &&
TARGET_FUSED_MADD"
+ "nmadd.s\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "SF")])
+
+(define_insn ""
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (minus:DF (match_dup 0)
+ (mult:DF (match_operand:DF 1 "register_operand" "f")
+ (match_operand:DF 2 "register_operand" "f"))))]
+ "(TARGET_LOONGSON2E || TARGET_LOONGSON2F) && TARGET_HARD_FLOAT &&
TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
+ "nmsub.d\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "DF")])
+
+(define_insn ""
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (minus:SF (match_dup 0)
+ (mult:SF (match_operand:SF 1 "register_operand" "f")
+ (match_operand:SF 2 "register_operand" "f"))))]
+ "(TARGET_LOONGSON2E || TARGET_LOONGSON2F) && TARGET_HARD_FLOAT &&
TARGET_FUSED_MADD"
+ "nmsub.s\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "SF")])
+
;;
;; ....................
@@ -2367,6 +2467,61 @@
;; ....................
;;
+;; For loongson
+
+(define_insn "divsi3"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (div:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")))]
+ "TARGET_LOONGSON2E || TARGET_LOONGSON2F"
+ { return mips_output_division_g ("div.g\t%0,%1,%2", operands); }
+ [(set_attr "type" "divg")
+ (set_attr "mode" "SI")
+ (set (attr "length")
+ (if_then_else (ne (symbol_ref "TARGET_CHECK_ZERO_DIV") (const_int 0))
+ (const_int 16)
+ (const_int 4)))])
+
+(define_insn "udivsi3"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (udiv:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")))]
+ "TARGET_LOONGSON2E || TARGET_LOONGSON2F"
+ { return mips_output_division_g ("divu.g\t%0,%1,%2", operands); }
+ [(set_attr "type" "divg")
+ (set_attr "mode" "SI")
+ (set (attr "length")
+ (if_then_else (ne (symbol_ref "TARGET_CHECK_ZERO_DIV") (const_int 0))
+ (const_int 16)
+ (const_int 4)))])
+
+(define_insn "modsi3"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (mod:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")))]
+ "TARGET_LOONGSON2E || TARGET_LOONGSON2F"
+ { return mips_output_division_g ("mod.g\t%0,%1,%2", operands); }
+ [(set_attr "type" "divg")
+ (set_attr "mode" "SI")
+ (set (attr "length")
+ (if_then_else (ne (symbol_ref "TARGET_CHECK_ZERO_DIV") (const_int 0))
+ (const_int 16)
+ (const_int 4)))])
+
+(define_insn "umodsi3"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (umod:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")))]
+ "TARGET_LOONGSON2E || TARGET_LOONGSON2F"
+ { return mips_output_division_g ("modu.g\t%0,%1,%2", operands); }
+ [(set_attr "type" "divg")
+ (set_attr "mode" "SI")
+ (set (attr "length")
+ (if_then_else (ne (symbol_ref "TARGET_CHECK_ZERO_DIV") (const_int 0))
+ (const_int 16)
+ (const_int 4)))])
+;;
+
(define_expand "divdf3"
[(set (match_operand:DF 0 "register_operand" "")
(div:DF (match_operand:DF 1 "reg_or_const_float_1_operand" "")
2008/4/22, Maxim Kuvyrkov <[EMAIL PROTECTED]>:
> Eric Fisher wrote:
> > hi
> >
> > Is there anyone working on the loongson support of gcc? I notice
> > that loongson has been added into the currently developing binutils.
> >
>
> Eric,
>
> I will start working on submitting Loongson patches developed at
> CodeSourcery next week. These patches include general support for Loongson
> 2E/2F CPUs, support for Loongson intrinsics, scheduling model and tuning
> bits.
>
> --
> Maxim Kuvyrkov
> CodeSourcery Inc.
>
