On Thu, Jun 19, 2008 at 03:50:34PM -0500, Joel Sherrill wrote:
> Andrew Pinski wrote:
> >On Thu, Jun 19, 2008 at 1:36 PM, Joel Sherrill
> ><[EMAIL PROTECTED]> wrote:
> >
> >>Hi,
> >>
> >>I ran into something tracking down a test
> >>failure on psim and now thing there is a
> >>target specific issue that needs addressing.
> >>
> >
> >lwsync is sync with the bit 9 set. So it should be ok as it was a
> >reserved field and was supposed to be ignored on the hardware which
> >did not implement those bits and have it as a sync (but I could be
> >wrong).
> >
> I don't have access to a real 603e of this vintage but
> my Sept 1995 603e User's Manual shows the sync
> instruction has having:
>
> 0-5 - all 1's (value in table is 31)
> 6-20 - all 0's (dark grey indicating not implemented)
> 21-30 - 598
> 31 - 0
>
I have 6 PPC603ev (5 at revision 2.1 and one at 18.1
according to /proc/cpuinfo, some of them running almost
nonstop for 11 years, all of them for 7 years at least)
and they all accept an:
asm volatile("lwsync" : : : "memory");
between two printf() without trapping (I see the output of
the second printf).
I also tried with ptesync, which is also accepted.
Regards,
Gabriel
