Luis Machado wrote:
Upon further investigation on facerec's regression, it looks like the
code generated by the IRA-enabled gcc has many more spills than the one
with a disabled IRA, twice or sometimes three times more.
I'm trying to reduce the testcase a bit further so it's simpler to
analyse.
I am working on this too, Luis. After a few day of analysis of applu
hot functions, I found one several hundred insn loop (fortunately it is
one basic block) in function jacu which contains 8 more insns that one
generated by old RA. The assigning made by IRA looks a bit better than
assigning made by the old RA. It seems to me that one problem is in
choosing best register to spill for reloads. The first heuristic is
based on cost of spill and IRA has choosen to spill register which is
set and used once in practically neighbor insns. Changing spill
heuristics based on cost to one based on priority defined as
log(NREFS) * cost / live_range_length_where_high_pressure_is_high
significantly improved SPECFP2000 and SPECINT2000 for power6 making them
better than for the old RA. Still there is performance degradation on
applu and facerec (although facerec improved about 2.5%). I'd commit
the patch but I think it is not ready yet because the new heuristic
worsen SPEC2000 for x86/x86_64. Probably we need different heuristics
for RISC and CISC machines (which permit memory as operands). I'll
think how to distinguish them.
I am going to look at facerec too. Only, please, don't expect all this
problem will be solved soon.
Vlad
