[Thanks to all those who responded to my previous problem-report wrt to the IEEE inexact-flag on the Alpha. We have filed a bug report for that one.]
Hi there, we keep finding problems on the Alpha, and we are unsure about what is going on. I anticipate that the present problem does not seem to be a compiler issue (except that the -mieee-with-inexact option promises full compliance with the IEEE floating point standard). However, I hope some Alpha expert can advise about how to investigate the issue further. Here are the details: $ cat bug.c #include <stdio.h> float f = 1.4e-45; double d = 1e-300; int main() { if (1.4e-45f > 1e-300) printf("compile-time test says 1.4e-45f > 1e-300\n"); if (f < d) printf(" run-time test says 1.4e-45f < 1e-300\n"); return 0; } $ gcc -mieee-with-inexact bug.c $ ./a.out compile-time test says 1.4e-45f > 1e-300 run-time test says 1.4e-45f < 1e-300 $ gcc -v Using built-in specs. Target: alpha-linux-gnu Configured with: ../src/configure -v --enable-languages=c,c++,fortran,objc,obj-c++ --prefix=/usr --enable-shared --with-system-zlib --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --enable-nls --with-gxx-include-dir=/usr/include/c++/4.2 --program-suffix=-4.2 --enable-clocale=gnu --enable-libstdcxx-debug --enable-objc-gc --enable-mpfr --disable-libssp --with-long-double-128 --enable-checking=release --build=alpha-linux-gnu --host=alpha-linux-gnu --target=alpha-linux-gnu Thread model: posix gcc version 4.2.4 (Debian 4.2.4-3) $ cat /proc/cpuinfo cpu : Alpha cpu model : EV56 cpu variation : 7 cpu revision : 0 cpu serial number : system type : Rawhide system variation : Tincup system revision : 0 system serial number : AY74642662 cycle frequency [Hz] : 399642346 est. timer frequency [Hz] : 1200.00 page size [bytes] : 8192 phys. address bits : 40 max. addr. space # : 127 BogoMIPS : 705.16 kernel unaligned acc : 0 (pc=0,va=0) user unaligned acc : 35 (pc=20000074c18,va=87) platform string : AlphaServer 1200 5/400 4MB cpus detected : 1 cpus active : 1 cpu active mask : 0000000000000001 L1 Icache : 8K, 1-way, 32b line L1 Dcache : 8K, 1-way, 32b line L2 cache : 96K, 3-way, 64b line L3 cache : 4096K, 1-way, 64b line All the best, Roberto -- Prof. Roberto Bagnara Computer Science Group Department of Mathematics, University of Parma, Italy http://www.cs.unipr.it/~bagnara/ mailto:[EMAIL PROTECTED]