I've got this code: (define_insn "andhi3_24" [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,*Rhl,*Rhl,RhiSd,??Rmm,RhiSd,??Rmm") (and:HI (match_operand:HI 1 "mra_operand" "%0,0,*0,*0,0,0,0,0") (match_operand:HI 2 "mrai_operand" "Imb,Imw,*Imb,*Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))] "TARGET_A24" "@ bclr\t%B2,%0 bclr\t%B2-8,1+%0 bclr\t%B2,%h0 bclr\t%B2-8,%H0 and.w\t%X2,%0 and.w\t%X2,%0 and.w\t%X2,%0 and.w\t%X2,%0" [(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")] )
Originally, the '*' constraints were missing. It failed: /greed/dj/ges/gnupro/head/gnupro/gcc/testsuite/gcc.c-torture/execute/pr17133.c: In function 'pure_alloc': /greed/dj/ges/gnupro/head/gnupro/gcc/testsuite/gcc.c-torture/execute/pr17133.c:19: error: unable to find a register to spill in class 'HL_REGS' /greed/dj/ges/gnupro/head/gnupro/gcc/testsuite/gcc.c-torture/execute/pr17133.c:19: error: this is the insn: (insn 31 30 32 6 /greed/dj/ges/gnupro/head/gnupro/gcc/testsuite/gcc.c-torture/execute/pr17133.c:13 (set (reg:HI 0 r0 [41]) (and:HI (subreg:HI (reg/f:PSI 5 a1 [orig:29 bar.0 ] [29]) 0) (const_int -2 [0xfffffffe]))) 26 {andhi3_24} (expr_list:REG_DEAD (reg/f:PSI 5 a1 [orig:29 bar.0 ] [29]) (nil))) /greed/dj/ges/gnupro/head/gnupro/gcc/testsuite/gcc.c-torture/execute/pr17133.c:19: internal compiler error: in spill_failure, at reload1.c:2093 I added the '*' constraints to keep it from using HL_REGS class (HL includes R0 and R1, HI includes R0 through R3) but it seems to be ignoring them. If I remove those alternatives completely, the code compiles properly. How can I get register allocation to use HI_REGS as the allocation class? I still want the bclr opcodes to be used *if* the constraints hold. I just don't want them to limit register choices. What am I missing?