I've finished the first round of testing on all targets and will be
sending patches soon.

Overall, I think the results are quite satisfying.

For the current bunch of files, I get the same code on the following
targets:

  m32c crx mmix xstormy16 fr30 v850 m32r iq2000 picochip mcore spu ia64
  m68hc11 alpha frv e500* arm

  * I'm treating e500 as a different target than powerpc

I get the same code except for unordered comparisons, which are
improved, on the following targets:

  mips sparc

I get the same code except for small scheduling changes with some option
combinations on the following targets:

  m68k i386 rs6000

I get the same code with small improvements in instruction selection or
delay slot scheduling on the following targets:

  vax avr cris h8300

I get slightly better code because of better optimization (especially if
conversion) on the following targets:

  arc xtensa mn10300 score bfin

I get large improvements on the following target:

  pdp11

I get overall a slight decrease in code quality, which is however offset
by patches to expand that I've already posted, on the following targets:

  pa s390


I have not yet converted sh.  I'll do so today.  Next step is simulator
testing for targets that, well, have a simulator.

I'll be posting the target conversion patches soon.  Indications about
the options that I tested will be found there.

The intention is to merge early in stage1 either as a series of commits
or just one or anything in the middle.

As usual, if people want me to switch to a public branch, just tell me.

Paolo

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