> From: Michael Meissner <meiss...@linux.vnet.ibm.com>
> To: Jamie Prescott <jpre...@yahoo.com>
> Cc: gcc@gcc.gnu.org
> Sent: Sunday, May 24, 2009 1:57:19 PM
> Subject: Re: Seeking suggestion
>
> One way is to use match_scratch, and different register classes for the two
> cases.
>
> (define_insn "add3"
> [(set (match_operand:SI 0 "register_operand" "=x,y")
> (plus:SI (match_operand:SI 1 "register_operand" "%x,y")
> (match_operand:SI 2 "register_operand" "x,y")))
> (clobber (match_scratch:CC 3 "=X,z"))]
> ""
> "add %0,%1,%2")
>
>
> (define_register_constraint "x" "TARGET_MACHINE ? GENERAL_REGS : NO_REGS"
> "@internal")
>
> (define_register_constraint "y" "!TARGET_MACHINE ? GENERAL_REGS : NO_REGS"
> "@internal")
>
> (define_register_constraint "z" CR_REGS "@interal")
>
> This assumes you have a register class for the condition code register. Most
> machines however, use the normal define_expand with two different insns.
>
> In theory, you could define a second condition code register that doesn't
> actually exist in the machine, and change the clobber from the main CC to the
> fake one.
Hmm, interesting. Thanks Michael.
Though, as you were saying, I'll probably leave them as separate insns. These
should
have been two separate targets probably, but I'm too lazy to split them up ATM.
> > But now I get and invalid rtx sharing from the push/pop parallels:
> >
> >
> > xxxx.c: In function 'test_dashr':
> > xxxx.c:32: error: invalid rtl sharing found in the insn
> > (insn 26 3 28 2 xxxx.c:26 (parallel [
> > (insn/f 25 0 0 (set (reg/f:SI 51 SP)
> > (minus:SI (reg/f:SI 51 SP)
> > (const_int 4 [0x4]))) -1 (nil))
> > (set/f (mem:SI (reg/f:SI 51 SP) [0 S4 A8])
> > (reg:SI 8 r8))
> > ]) -1 (nil))
> > xxxx.c:32: error: shared rtx
> > (insn/f 25 0 0 (set (reg/f:SI 51 SP)
> > (minus:SI (reg/f:SI 51 SP)
> > (const_int 4 [0x4]))) -1 (nil))
> > xxxx.c:32: internal compiler error: internal consistency failure
>
> I suspect you don't have the proper guards on the push/pop insns, and the
> combiner is eliminating the clobber. You probably need to have parallel insns
> for the push and pop.
Dunno exactly what was happening. The push/pop were generated with a parallel,
but I was issuing a gen_addsi3() directly, and this somehow was creating the
problem.
Once I open coded that with SET(SP, PLUS(SP, SIZE)), the issue disappeared.
- Jamie
