On Thu, 2009-09-17 at 21:48 -0700, Ian Lance Taylor wrote: > "Amker.Cheng" <amker.ch...@gmail.com> writes: > > > Recently I found two relative old papers about non-blocking cache, > > etc. which are : > > > > 1) Reducing memory latency via non-blocking and prefetching > > caches. BY Tien-Fu Chen and Jean-Loup Baer. > > 2) Data Prefetching:A Cost/Performance Analysis BY Chris Metcalf > > > > It seems the hardware facility does have the potential to improve the > > performance with > > compiler's assistance(especially instruction scheduling). while on the > > other hand, lifting ahead > > load instructions may resulting in increasing register pressure. > > > > So I'm thinking : > > 1, Has anyone from gcc folks done any investigation on this topic yet, > > or any statistic data based on gcc available? > > 2, Does GCC(in any release version) supports it in any targets(such as > > mips 24ke) with this hardware feature? > > If not currently, does it possible to support it by using target > > definition macros and functions? > > gcc is able to generate prefetches in loops, via the > -fprefetch-loop-arrays option. There are various related parameters, > prefetch-latency, l1-cache-line-size, etc. I don't know how well this > works. To the extent that it does work, it is supported in the MIPS > backend, and should work on the MIPS 24ke.
There's also a prefetch built-in function; see http://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html#Other-Builtins It's been in GCC since 3.1. Janis
