Thanks for explanation. here are three more questions 1 , If I am talking the right thing, there are two insns like "*mulsi3_1" and "*smulsi3_highpart_insn", which set two parts of DImode pseudo regs of DImode mult.
Since both parts pf result are used in the original example, I am not sure how to make split pattern to handle this case without generating two duplicate mult insns in parallel. 2 , If I could set the two parts of result in parallel insn, I also have to handle mips specific constraints in this case, i.e, constraints for HI/LO registers. Unfortunately, There is no "h" constraint now according to patch http://gcc.gnu.org/ml/gcc-patches/2008-05/msg01750.html It is not possible to write hi reg without clobbering the lo reg now, How should I handle this? 3 , Since I am studying IRA right now, I am very curious about whether possible to solve this in IRA. e.g, by shrinking live ranges of multi-word pseudo regs? PS, maybe I am talking gibberish, Sorry If not clear enough. Thanks. -- Best Regards.