In this example, why isn't insn 117 scheduled before insn 115 ? What is the dependency? The only thing they have in common is CC, but both generate a value which is never used.
;; ====================================================== ;; -- basic block 15 from 114 to 118 -- after reload ;; ====================================================== ;; dependencies resolved: insn 114 ;; tick updated: insn 114 into ready ;; Ready list after queue_to_ready: 114:46 ;; Ready list after ready_sort: 114:46 ;; Ready list (t = 0): 114:46 ;; 0--> 114 r12=sxn([r14]) :throughput,nothing ;; dependencies resolved: insn 115 ;; Ready-->Q: insn 115: queued for 2 cycles. ;; tick updated: insn 115 into queue with cost=2 ;; Ready list (t = 0): ;; Q-->Ready: insn 115: moving to ready with 1 stalls ;; Ready list after queue_to_ready: 115:47 ;; Ready list after ready_sort: 115:47 ;; Ready list (t = 2): 115:47 ;; 2--> 115 {r12=r3+r12;cc=cmp(r3+r12,0x0);} :throughput ;; dependencies resolved: insn 116 ;; Ready-->Q: insn 116: queued for 1 cycles. ;; tick updated: insn 116 into queue with cost=1 ;; dependencies resolved: insn 117 ;; Ready-->Q: insn 117: queued for 1 cycles. ;; tick updated: insn 117 into queue with cost=1 ;; Ready list (t = 2): ;; Q-->Ready: insn 117: moving to ready without stalls ;; Q-->Ready: insn 116: moving to ready without stalls ;; Ready list after queue_to_ready: 116:49 117:48 ;; Ready list after ready_sort: 116:49 117:48 ;; Ready list (t = 3): 116:49 117:48 ;; 3--> 117 {r4=r4+0x1;cc=cmp(r4+0x1,0x0);} :throughput ;; Ready list (t = 3): 116:49 ;; Ready list after queue_to_ready: 116:49 ;; Ready list after ready_sort: 116:49 ;; Ready list (t = 4): 116:49 ;; 4--> 116 [r14]=r12 :throughput ;; dependencies resolved: insn 118 ;; tick updated: insn 118 into ready ;; Ready list (t = 4): 118:50 ;; Ready list after queue_to_ready: 118:50 ;; Ready list after ready_sort: 118:50 ;; Ready list (t = 5): 118:50 ;; 5--> 118 {r14=r14+0x2;cc=cmp(r14+0x2,0x0);}:throughput ;; Ready list (t = 5): ;; Ready list (final): ;; total time = 5 ;; new head = 114 ;; new tail = 118 ;; Start of basic block ( 14 9) -> 15 ;; bb 15 artificial_defs: { } ;; bb 15 artificial_uses: { u-1(0){ }} ;; lr in 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 7 [r7] 11 [r11] 14 [r14] 15 [r15] ;; lr use 0 [r0] 3 [r3] 4 [r4] 14 [r14] ;; lr def 4 [r4] 12 [r12] 14 [r14] 16 [cc] ;; live in 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 7 [r7] 11 [r11] 14 [r14] 15 [r15] ;; live gen 4 [r4] 12 [r12] 14 [r14] 16 [cc] ;; live kill ;; Pred edge 14 [100.0%] (fallthru,can_fallthru) ;; Pred edge 9 [25.0%] (can_fallthru) (code_label 311 102 120 15 1121 "" [1 uses]) (note 120 311 113 15 [bb 15] NOTE_INSN_BASIC_BLOCK) (note 113 120 114 15 NOTE_INSN_DELETED) (insn 114 113 115 15 dj.c:256 (set (reg:SI 12 r12 [138]) (sign_extend:SI (mem:HI (reg:SI 14 r14 [orig:24 ivtmp.929 ] [24]) [2 S2 A16]))) 60 {extendhisi2} (nil)) (insn 115 114 117 15 dj.c:256 (parallel [ (set (reg:SI 12 r12 [139]) (plus:SI (reg:SI 3 r3 [orig:54 pretmp.923 ] [54]) (reg:SI 12 r12 [138]))) (set (reg:CC_ZSC 16 cc) (compare:CC_ZSC (plus:SI (reg:SI 3 r3 [orig:54 pretmp.923 ] [54]) (reg:SI 12 r12 [138])) (const_int 0))) ]) 72 {addsi3} (expr_list:REG_UNUSED (reg:CC_ZSC 16 cc) (nil))) (insn 117 115 116 15 dj.c:255 (parallel [ (set (reg/v:SI 4 r4 [orig:31 j ] [31]) (plus:SI (reg/v:SI 4 r4 [orig:31 j ] [31]) (const_int 1))) (set (reg:CC_ZSC 16 cc) (compare:CC_ZSC (plus:SI (reg/v:SI 4 r4 [orig:31 j ] [31]) (const_int 1)) (const_int 0))) ]) 72 {addsi3} (expr_list:REG_UNUSED (reg:CC_ZSC 16 cc) (nil))) (insn 116 117 118 15 dj.c:256 (set (mem:HI (reg:SI 14 r14 [orig:24 ivtmp.929 ] [24]) [2 S2 A16]) (reg:HI 12 r12 [139])) 58 {*movhi_internal} (expr_list:REG_DEAD (reg:HI 12 r12 [139]) (nil))) (insn 118 116 310 15 dj.c:255 (parallel [ (set (reg:SI 14 r14 [orig:24 ivtmp.929 ] [24]) (plus:SI (reg:SI 14 r14 [orig:24 ivtmp.929 ] [24]) (const_int 2))) (set (reg:CC_ZSC 16 cc) (compare:CC_ZSC (plus:SI (reg:SI 14 r14 [orig:24 ivtmp.929 ] [24]) (const_int 2)) (const_int 0))) ]) 72 {addsi3} (expr_list:REG_UNUSED (reg:CC_ZSC 16 cc) (nil))) ;; End of basic block 15 -> ( 16) ;; lr out 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 7 [r7] 11 [r11] 14 [r14] 15 [r15] ;; live out 0 [r0] 1 [r1] 2 [r2] 3 [r3] 4 [r4] 7 [r7] 11 [r11] 14 [r14] 15 [r15]