On Sun, Sep 11, 2011 at 03:00:11PM -0400, Geert Bosch wrote: > Also, for relaxed order atomic operations we would only need a single > fence between two accesses (by a thread) to the same atomic object.
I'm not aware of any CPUs that would need any kind of fences for that.
Nor the compiler should need any fences for that, MEMs that may (or even are
known to be aliased) aren't reordered.
Jakub
