Ben Morgan <benm.mor...@gmail.com> writes: > In a course at my university (Universität Würzburg, Germany) we have > created a 32-bit RISC CPU architecture -- the HaDesXI-CPU -- (in VHDL) > which we then play onto a FPGA (the Xilinx Spartan-3AN) to use. So far > if we want to do anything with it, we have to write the assembly code > ourselves. > > How much work would it be to write a HadesXI backend for GCC? > (The idea is to use this as a possible bachelor thesis.) > > Where would be a good place to start; what are the prerequisites for > undertaking a project like this other than knowing the CPU architecture > inside out?
The difficulty depends entirely on the characteristics of the CPU and the extent to which you want GCC to take advantage of any unusual features. I've seen other messages commenting on the length of time and the difficulties of the internal docs, but I think they are exaggerating the problems. Porting a new CPU is the best documented part of GCC internals. My rule of thumb for an experienced toolchain programmer to add a complete GNU toolchain port--compiler, assembler, linker, debugger--is three months. The compiler alone is about half that. Other than knowing the CPU, the prerequisite is the ability to read and understand the GCC internal docs, the willingness to look at other GCC ports for similar processors, and the willingness to write code. It's worth looking at Anthony Green's blog about implementing moxie at http://moxielogic.org/ , as he described the process of doing a full GCC port. I don't know what a bachelor thesis is, so I don't know if this would be suitable. A GCC port by itself would be too simple for a masters thesis in the U.S. Ian
