Hello,
A "Not yet implemented" comment in reorg.c discusses conditional
execution. The comment already existed in the earliest revision in the
repository (r99) so it pre-dates the conditional execution framework
now used by the "Acorn RISC Machine" (better known as ARM nowadays :-)
and how HP-PA can do something similar.
The comment in reorg.c looks out of place now, and the ability of
PA-RISC to nullify instructions isn't mentioned anywhere. AFAICT GCC
does not exploit this ability so I've added a comment for a suggested
improvement in pa.md.
OK for trunk?
Ciao!
Steven
* reorg.c: Remove obsolete comment.
* config/pa/pa.md: Add comment explaining how PA-RISC allows most
instructions to nullify the immediately following instruction.
Index: reorg.c
===================================================================
--- reorg.c (revision 193787)
+++ reorg.c (working copy)
@@ -100,16 +100,7 @@ along with GCC; see the file COPYING3.
delay slot. In that case, we point each insn at the other with REG_CC_USER
and REG_CC_SETTER notes. Note that these restrictions affect very few
machines because most RISC machines with delay slots will not use CC0
- (the RT is the only known exception at this point).
-
- Not yet implemented:
-
- The Acorn Risc Machine can conditionally execute most insns, so
- it is profitable to move single insns into a position to execute
- based on the condition code of the previous insn.
-
- The HP-PA can conditionally nullify insns, providing a similar
- effect to the ARM, differing mostly in which insn is "in charge". */
+ (the RT is the only known exception at this point). */
#include "config.h"
#include "system.h"
Index: config/pa/pa.md
===================================================================
--- config/pa/pa.md (revision 193786)
+++ config/pa/pa.md (working copy)
@@ -1,6 +1,5 @@
;;- Machine description for HP PA-RISC architecture for GCC compiler
-;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
-;; 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
+;; Copyright (C) 1992-2012
;; Free Software Foundation, Inc.
;; Contributed by the Center for Software Science at the University
;; of Utah.
@@ -21,8 +20,31 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
-;; This gcc Version 2 machine description is inspired by sparc.md and
-;; mips.md.
+;; This machine description is inspired by sparc.md and (to a lesser
+;; extend) mips.md.
+
+;; Possible improvements, if anyone is still interested in working on
+;; improving this machine description in 2012:
+;;
+;; * With PA2.0, most computational instructions can conditionally nullify
+;; the execution of the following instruction. Nullification is performed
+;; conditionally based on the outcome of a test specified in the opcode.
+;; The test result is stored in PSW[N] and can only be used to nullify the
+;; instruction following immediately after the test. For example:
+;;
+;; ldi 10,%r26 ldi 10,%r26
+;; ldi 5,%r25 ldi 5,%r25
+;; sub,< %r26,%r25,%r28 sub,> %r26,%r25,%r28
+;; sub %r28,%r25,%r28 sub %r28,%r25,%r28
+;; ; %r28 == 0 ; %r28 == 5
+;;
+;; This could be tricky to implement because the result of the test has
+;; to be propagated one instruction forward, which, in the worst case,
+;; would involve (1) adding a fake register for PSW[N]; (2) adding the
+;; variants of the computational instructions that set or consume this
+;; fake register. The cond_exec infrastructure is probably not helpful
+;; for this.
+;;
;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
