I have an instruction scheduling question I was hoping someone could help me
with. Specifically, I am trying to figure out where and how GCC is deciding
to move the add of a constant to a register above the use of that register and
then changing the register usage by change the offsets associated with it.
For example, I am compiling the following memcpy code for MIPS:
void *memcpy_word_ptr(int * __restrict d, int * __restrict s, unsigned int n )
{
int i;
for(i=0; i<n; i++) *d++ = *s++;
return d;
}
Using -fno-tree-loop-distribute-patterns -funroll-loops -O3,
the main loop I get is:
.L4:
lw $13,0($7)
addiu $7,$7,32
addiu $3,$3,32
addiu $8,$8,8
lw $12,-28($7)
lw $14,-24($7)
lw $15,-20($7)
lw $24,-16($7)
lw $5,-12($7)
lw $25,-8($7)
lw $9,-4($7)
sw $13,-32($3)
sw $12,-28($3)
sw $14,-24($3)
sw $15,-20($3)
sw $24,-16($3)
sw $5,-12($3)
sw $25,-8($3)
bne $8,$6,.L4
sw $9,-4($3)
Now, if I turn off instruction scheduling (-fno-schedule-insns
-fno-schedule-insns2), I get:
.L4:
lw $11,0($7)
sw $11,0($3)
lw $12,4($7)
sw $12,4($3)
lw $13,8($7)
sw $13,8($3)
lw $14,12($7)
sw $14,12($3)
lw $5,16($7)
sw $5,16($3)
lw $15,20($7)
sw $15,20($3)
lw $24,24($7)
sw $24,24($3)
addiu $3,$3,32
addiu $7,$7,32
lw $25,-4($7)
addiu $8,$8,8
bne $8,$6,.L4
sw $25,-4($3)
The part of the scheduling change that I am interested in is the change in
where the addiu instruction occurs and the related changes from the positive
offsets to the negative offsets. Can anyone tell me where the code that
decides to do that is? Extra bonus points for any answer not including the
word 'reload'.
Steve Ellcey
sell...@mips.com
