On 03/27/2014 02:50 PM, Felix Yang wrote:
I find DCE in sched2 is disabled for C6X backend. Is this a
performance consideration? Or a GCC BUG?
As far as I remember, it's a problem due to how delayed instructions are
represented to the final scheduler. Just before that scheduling pass is
run, the actual instruction is turned into just an UNSPEC without
visible side effects, and a shadow insn that describes the side effect
is created. The scheduler ensures that the shadow insn always occurs
after a fixed time from the real insn (set up by record_delay_slot_pair).
Any pass other than the scheduler would be confused by this
representation (and by the delayed effects in general), that includes DCE.
Bernd
