> I gather that r0 is the stack pointer and r6 the frame pointer?
Yes.
> > 00000014 00000030 00000000 FDE cie=00000000 pc=00000000..00000043
> > DW_CFA_advance_loc4: 2 to 00000002
> > DW_CFA_def_cfa_offset: 32
> > DW_CFA_offset: r12 at cfa-8
> > . . .
> > DW_CFA_offset: r6 at cfa-32
> > DW_CFA_advance_loc4: 3 to 00000005
> > DW_CFA_def_cfa: r6 ofs 36
> > DW_CFA_advance_loc4: 2 to 00000007
> > DW_CFA_def_cfa_register: r0
> > ( that's it for debug info )
>
> If so, the above DW_CFA_def_cfa_register doesn't make sense, it should be r6
> once the frame is established. What does the CIE contain exactly?
00000000 00000010 ffffffff CIE
Version: 3
Augmentation: ""
Code alignment factor: 1
Data alignment factor: -4
Return address column: 17
DW_CFA_def_cfa: r0 ofs 4
DW_CFA_offset: r17 at cfa-4
DW_CFA_nop
DW_CFA_nop
00000014 00000030 00000000 FDE cie=00000000 pc=00000000..00000043
DW_CFA_advance_loc4: 2 to 00000002
DW_CFA_def_cfa_offset: 32
DW_CFA_offset: r12 at cfa-8
DW_CFA_offset: r11 at cfa-12
DW_CFA_offset: r10 at cfa-16
DW_CFA_offset: r9 at cfa-20
DW_CFA_offset: r8 at cfa-24
DW_CFA_offset: r7 at cfa-28
DW_CFA_offset: r6 at cfa-32
DW_CFA_advance_loc4: 3 to 00000005
DW_CFA_def_cfa: r6 ofs 36
DW_CFA_advance_loc4: 2 to 00000007
DW_CFA_def_cfa_register: r0
> > Perhaps the stack-check code should set FRAME_RELATED on any stack
> > adjustment insn?
>
> No, the design is that stack checking or alloca force the use of the frame
> pointer, which thus becomes the CFA register, which means that subsequent
> stack adjustments are irrelevant for the CFI.
Does the backend have to *not* mark further changes to the stack
pointer in the prologue as frame related, if the function calls
alloca? This is the RL expand_prologue() is emitting:
(insn/f 42 5 43 2 (parallel [
(set/f (reg/f:SI 0 r0)
(minus:SI (reg/f:SI 0 r0)
(const_int 28 [0x1c])))
(set/f (mem:SI (minus:SI (reg/f:SI 0 r0)
(const_int 4 [0x4])) [0 S4 A8])
(reg:SI 12 r12))
(set/f (mem:SI (minus:SI (reg/f:SI 0 r0)
(const_int 8 [0x8])) [0 S4 A8])
(reg:SI 11 r11))
(set/f (mem:SI (minus:SI (reg/f:SI 0 r0)
(const_int 12 [0xc])) [0 S4 A8])
(reg:SI 10 r10))
(set/f (mem:SI (minus:SI (reg/f:SI 0 r0)
(const_int 16 [0x10])) [0 S4 A8])
(reg:SI 9 r9))
(set/f (mem:SI (minus:SI (reg/f:SI 0 r0)
(const_int 20 [0x14])) [0 S4 A8])
(reg:SI 8 r8))
(set/f (mem:SI (minus:SI (reg/f:SI 0 r0)
(const_int 24 [0x18])) [0 S4 A8])
(reg/f:SI 7 r7))
(set/f (mem:SI (minus:SI (reg/f:SI 0 r0)
(const_int 28 [0x1c])) [0 S4 A8])
(reg/f:SI 6 r6))
]) dj.c:2 -1
(nil))
(insn/f 43 42 44 2 (parallel [
(set (reg/f:SI 6 r6)
(plus:SI (reg/f:SI 0 r0)
(const_int -4 [0xfffffffffffffffc])))
(clobber (reg:CC 16 cc))
]) dj.c:2 -1
(nil))
(insn/f 44 43 45 2 (set (reg/f:SI 0 r0)
(reg/f:SI 6 r6)) dj.c:2 -1
(nil))
