On Fri, Apr 24, 2015 at 12:09 PM, Ilya Enkovich <enkovich....@gmail.com> wrote:
>>>> I was looking into PR65105 and tried to generate SSE computation for a >>>> simple 64bit a + b + c sequence. Having no scalar integer instructions in >>>> SSE I have to use vector variants. >>> >>> Is this approach really better that having two add/addc instructions? >> >> FYI, V1DI mode was introduced because XMM shift insn were used to >> shift DImode values. The cost of moves from/to integer DImode reg pair >> was disastrous. >> >> Uros. > > Does it mean I have to add V1DI instructions for all opcodes I want to > transform (add,sub,mul,or,and, etc.)? No. Please try to generate paradoxical subreg (V2DImode subreg of V1DImode pseudo). IIRC, there is some functionality in the compiler that is able to tell if the highpart of the paradoxical register is zeroed. Uros.
