On Mon, May 04, 2015 at 12:33:38PM -0700, Richard Henderson wrote: > (1) Each target defines a set of constraint strings,
> (2) A new target hook post-processes the asm_insn, looking for the > new constraint strings. The hook expands the condition prescribed > by the string, adjusting the asm_insn as required. Since it is pre-processed, there is no real reason to overlap this with the constraints namespace; we could have e.g. "=@[xy]" (and "@[xy]" for inputs) mean the target needs to do some "xy" transform here. > Note that the output constraints are adjusted to a single internal "=j_" > which would match the flags register in any mode. We can collapse > several output flags to a single set of the flags hard register. Many targets would use an already existing contraint that describes the flags. Targets that need a fixed register could just insert the hard register here as far as I see? (I'm assuming this happens at expand time). > (3) Note that ppc is both easier and more complicated. > > There we have 8 4-bit registers, although most of the integer > non-comparisons only write to CR0. And the vector non-comparisons > only write to CR1, though of course that's of less interest in the > context of kernel code. > > For the purposes of cr0, the same scheme could certainly work, although > the hook would not insert a hard register use, but rather a pseudo to > be allocated to cr0 (constaint "x"). And "y" for "any CR field". > That said, it's my understanding that "dot insns", setting cr0 are > expensive in current processor generations. They are not. (Cell BE is not "current" :-) ) PowerPC also has some other bits (the carry bit for example, CA) that could be usefully exposed via this mechanism. > Can anyone think of any drawbacks, pitfalls, or portability issues to less > popular targets that I havn't considered? I don't like co-opting the constraint names for this; other than that, it looks quite good :-) Segher
