This message describes the arrangement of the patches on the SVE branch.
We've tried to make them fit a plausible submission order, with each
patch having its own covering note and rationale (but no changelog :-)).
They should also be bisect-friendly.
The patches break down into the following broad stages:
A. General fixes
These patches fix bugs or accidental missed optimisations that aren’t
directly related to SVE. Usually the changes were done as part of
general SVE work and it only became clear later that they were fixing
real rather than theoretical problems.
The baseline is a couple of weeks old now and at least one these
issues has already been fixed on trunk.
Patches covered:
"Move misplaced assignment in num_sign_bit_copies1"
...
"Use df_read_modify_subreg_p in cprop.c"
B. Prepare for machine mode changes
These patches fix preexisting problems that would trigger an ICE with
the patches from stage C. They don’t appear to have any independent
effect on code generation.
Patches covered:
"Add more subreg offset helpers"
...
"Set mode of decimal floats before calling layout_type"
C. Rework the handling of machine modes
These patches add wrapper classes around the machine_mode enum for
situations in which the mode has known properties, as described in
the earlier message about variable mode sizes.
Patches covered:
"Add an E_ prefix to mode names and update case statements"
...
"Widening optab cleanup"
D. Prepare for the introduction of polynomial integers
These patches fix various problems that would cause build failures
with the patches from stage F. They also rework interfaces to make F
possible, including partial conversions of some macros to target hooks.
Patches covered:
"Add a full_integral_type_p helper function"
...
"Pass slp_index down to vect_analyze_stmt"
E. Add new tree and rtl constructs for representing variable-length vectors
These patches add a tree VEC_DUPLICATE_EXPR to go alongside the
existing rtl code VEC_DUPLICATE. They also add codes for creating
linear series and allow both duplicate and series constants to be
treated as gimple values.
Patches covered:
"Add rtx const vec_duplicate helpers"
...
"Treat VEC_{DUPLICATE,SERIES}_EXPR as gimple constants"
F. Add and use a "polynomial integer" class
These patches add a class to represent integers of the form C0 + C1*X1
+ ... + Cn*Xn, where each Ci is a compile-time constant and each
indeterminate Xi is a runtime parameter. See the earlier message
about variable mode sizes for more details.
Patches covered:
"Add poly-int.h"
...
"Use poly_int rtx accessors instead of hwi accessors"
G. Tweak the subreg rules
These patches divide SUBREG_REGs into REMODE_NATURAL_SIZE-sized
independently-addressable chunks rather than UNITS_PER_WORD-sized
independently-addressable chunks. This is a no-op for most targets
since the default value of REGMODE_NATURAL_SIZE is UNITS_PER_WORD.
The only existing target to override it is 64-bit SPARC, where this
appears to be a very minor improvement.
Patches covered:
"Base subreg rules on REGMODE_NATURAL_SIZE rather than UNITS_PER_WORD"
"Prevent invalid register mode changes in combine"
H. Prepare for the SVE port
These patches make various changes needed before a working SVE port
can be added. They subdivide into target-independent changes and
AArch64-specific changes.
Patches covered:
"Fix type of bitstart in vectorizable_live_operation"
...
"Improve vector mask pattern handling"
"[AArch64] Move code around"
...
"[AArch64] Tighten address register subreg checks"
I. Add the core SVE port
This stage contains a single patch that adds the core SVE port.
It supports existing vectorisation techniques with variable-length
vectors, with some restrictions.
Patch covered:
"[AArch64] Add SVE support"
J. Add additional SVE support
These patches add support for new vectorisation features and improve
the quality of the code produced for SVE in other areas (mainly ivopts).
Patches covered:
"Fix folding of vector mask EQ/NE expressions"
...
"vect.exp testsuite changes for SVE"
I compiled the GCC testsuite on at least one target per CPU architecture
to check that there were no accidental changes in assembly code between the
end of A (which is expected to change code generation) and the end of G.
Thanks,
Richard
