On Wed, 15 Mar 2017, Andrew Jenner wrote: > > I am assuming SPE and VLE do not support AltiVec or 64-bit PowerPC, > > please correct me if that is incorrect. Also, is "normal" floating > > point supported at all? > > My understanding is that SPE is only present in the e500v1, e500v2 and > e200z[3-7] cores, all of which are 32-bit only and do not have classic > floating-point units. SPE and Altivec cannot coexist as they have some > overlapping instruction encodings. The successor to e500v2 (e500mc) reinstated > classic floating-point and got rid of SPE.
The VLE ISA does support 64-bit implementations, using the same binary instruction encodings for 64-bit operations as the regular Power ISA (e.g. ldx, ldux, etc.), though I have no idea if such hardware actually exists or has been planned. > > Do some of those also support PowerPC? > > All the e200 cores apart from e200z0 can execute 32-bit instructions as well > as VLE, though we'll always generate VLE code when targetting them (otherwise > they're fairly standard). Many regular Power ISA binary instruction encodings are also supported in the VLE mode, especially where a replacement VLE encoding has not been invented. These include all 3-argument register ALU operations and many more (e.g. stbx, stbux, etc.). The VLE PEM lists over 100 regular Power instruction encodings retained (not counting optional 64-bit operations). So it's not that the VLE instruction set only shares mnemonics with the regular Power instruction set. In fact the opposite is the case: all the mnemonics that have been retained assemble to the same binary machine instructions, then some mnemonics (and their corresponding binary encodings) have been removed and some added (these are prefixed with `e_' for 32-bit binary encodings and `se_' for 16-bit ones). This intersection of the instruction sets was one motivation for keeping the ports together. FWIW, Maciej
