On Mon, Feb 26, 2018 at 8:15 PM, Florian Weimer <fwei...@redhat.com> wrote: > On 02/26/2018 05:00 AM, Ruslan Nikolaev via gcc wrote: >> >> If I understand correctly, the redirection to libatomic was made for 2 >> reasons: >> 1. cmpxchg16b is not available on early amd64 processors. (However, mcx16 >> flag already specifies that you use CPUs that have this instruction, so it >> should not be a concern when the flag is specified.) >> 2. atomic_load on read-only memory. > > > I think x86-64 should be able to do atomic load and store via SSE2 > registers,
There is no such architectural guarantee. At least on some micro-architecture (AMD Opteron "Istanbul") it's possible to construct a test which fails, proving that at least on that micro-arch SSE2 load/store isn't guaranteed to be atomic. See https://stackoverflow.com/questions/7646018/sse-instructions-which-cpus-can-do-atomic-16b-memory-operations/7647825 for more discussion and a testcase. -- Janne Blomqvist
