> On Sep 3, 2018, at 12:10 PM, Matthew Malcomson <matthew.malcom...@arm.com>
> wrote:
>
>>
>> I think you can use pdp11 as an example, it does two things that are similar
>> to what you're describing.
>>
>> One is that it requires SImode to go into an even regno, and indicates that
>> it uses two registers. See TARGET_HARD_REGNO_MODE_OK and
>> TARGET_HARD_REGNO_NREGS.
>>
>> The other is that it has one instruction that wants an odd (!) register: 16
>> bit multiply. Multiply is weird: if you give it an even destination
>> register it produces a 32 bit result in that register pair, with an odd
>> register number it produces a 16 bit result. So pdp11.md defines both
>> "mulhi3" and "mulsihi3" insns. The latter has an SImode output so that uses
>> the even numbered register, as I already described. The former uses a
>> machine-specific constraint "d". That is defined in constraints.md to mean a
>> register in class MUL_REGS. pdp11.h defines that name and what registers it
>> refers to, and pdp11.h does the reverse mapping (REGNO_REG_CLASS).
>>
>> If you want even register numbers for some instructions but that's not tied
>> to a specific type size (like SImode in my case), I think you'd want to use
>> something analogous to the MUL_REGS thing I described. Say, "EVEN_REGS".
>> REGNO_REG_CLASS would report even regnum to be in EVEN_REGS, odd in
>> GENERAL_REGS. The bitmaps for REG_CLASS_CONTENTS would show that EVEN_REGS
>> contains only even numbered registers while GENERAL_REGS contains both odd
>> and even. And you'd defined a register constraint which matches EVEN_REGS.
>> Then the instructions where you want them would use that constraint.
>>
>> paul
>>
>
>> Yes, it's possible. You can look at TDmode (128-bit decimal floating point)
>> on powerpc64*-linux, which is only allowed in even-odd register pairs.
>> It's in *all* cases though, not some of the time.
>>
>> Peter
>>
>
> Thanks for the suggestions,
> I've had a look into these, and unfortunately it seems they have the same
> problem I've been hitting before.
>
> The use of the TARGET_HARD_REGNO_MODE_OK macro limits all uses of registers
> in a given mode (so that we wouldn't be able to use register pairs beginning
> with odd registers for other instructions), while using an EVEN_REGS register
> class won't work in modes that span more than one hard register (as all hard
> registers covered by a pseudo register must be in the same class).
Is that so? I don't remember that restriction, and certainly pdp11 does not do
this. Could that be why LRA is failing in some of my tests? The "old" reload
pass makes no objections.
Note though that there are two possible ways to look at this.
1. Is there a register class such that all of the hard registers for a given
mode are in that class?
2. Is the value returned by REGNO_REG_CLASS the same for each of the hard
registers of a register pair?
For pdp11, (1) is true (they are both members of GENERAL_REGS) while (2) is
false (for the even register, GENERAL_REGS is returned, vs. MUL_REGS for the
odd one).
paul
