On Tue, 1 Dec 2020 at 16:39, Richard Biener <rguent...@suse.de> wrote: > > On Tue, 1 Dec 2020, Prathamesh Kulkarni wrote: > > > Hi, > > For the test mentioned in PR, I was trying to see if we could do > > specialized expansion for vcond in target when operands are -1 and 0. > > arm_expand_vcond gets the following operands: > > (reg:V8QI 113 [ _2 ]) > > (reg:V8QI 117) > > (reg:V8QI 118) > > (lt (reg/v:V8QI 115 [ a ]) > > (reg/v:V8QI 116 [ b ])) > > (reg/v:V8QI 115 [ a ]) > > (reg/v:V8QI 116 [ b ]) > > > > where r117 and r118 are set to vector constants -1 and 0 respectively. > > However, I am not sure if there's a way to check if the register is > > constant during expansion time (since we don't have df analysis yet) ? > > > > Alternatively, should we add a target hook that returns true if the > > result of vector comparison is set to all-ones or all-zeros, and then > > use this hook in gimple ISEL to effectively turn VEC_COND_EXPR into nop ? > > Would everything match-up for a .VEC_CMP IFN producing a non-mask > vector type? ISEL could special case the a ? -1 : 0 case this way. I think the vec_cmp pattern matches but it produces a masked vector type. In the attached patch, I simply replaced: _1 = a < b x = _1 ? -1 : 0 with x = view_convert_expr<_1>
For the test-case, isel generates:
vector(8) <signed-boolean:8> _1;
vector(8) signed char _2;
uint8x8_t _5;
<bb 2> [local count: 1073741824]:
_1 = a_3(D) < b_4(D);
_2 = VIEW_CONVERT_EXPR<vector(8) signed char>(_1);
_5 = VIEW_CONVERT_EXPR<uint8x8_t>(_2);
return _5;
and results in desired code-gen:
f1:
vcgt.s8 d0, d1, d0
bx lr
Altho I guess, we should remove the redundant conversions during isel itself ?
and result in:
_1 = a_3(D) < b_4(D)
_5 = VIEW_CONVERT_EXPR<uint8x8_t>(_1)
(Patch is lightly tested with only vect.exp)
Thanks,
Prathamesh
>
> > Thanks,
> > Prathamesh
> >
>
> --
> Richard Biener <rguent...@suse.de>
> SUSE Software Solutions Germany GmbH, Maxfeldstrasse 5, 90409 Nuernberg,
> Germany; GF: Felix Imendörffer; HRB 36809 (AG Nuernberg)
pr97282-1.diff
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