Jan wrote: >Tom Hawkins wrote: >> >> The interesting aspect of behavioral and transaction level modeling is >> there are now tools on the market to synthesize these higher abstraction >> levels. When will gEDA follow, I wonder? > > Which are those tools that should be followed? As you say 'now' I > assume you don't mean behaviorial synthesis, as that has been > available for a considerable time (but never became very popular).
Yes, behavioral is one, but not from HDL. Many vendors are now synthesizing from C and SystemC. It appears to work well for datapath intensive designs (DSP). For control-path oriented designs, Bluespec can synthesize transaction level models (TLM) from SystemVerilog mixed with their own guarded atomic actions. > >> Though Confluence is an RTL language, it obtains an abstraction level >> higher than Verilog/VHDL do to its functional programming >> characteristics (higher-order datatypes, lexical scoping, referential >> transparency, etc.). > > Perhaps, but if I understand it correctly it does this by abstracting away > features such as event driven semantics and procedural constructs, which > make it only applicable for a very specific kind of applications. For example, > not for systems with multiple clocks. So the comparison may be misleading. Confluence is free from event driven semantics and procedural constructs. And yes, it does handle multiple clocks. But the real abstractions come from the higher-order datatypes; in particular, first-class closures. In Verilog-speak, think of them as modules that can enter, or exit, other modules through ports. A bit weird at first, yet extremely powerful. -Tom
