On Wed, 16 Feb 2005, Nikolay V. Pyatkov wrote: > What should be the output of the program below in absolutely correct verilog > simulator? > > Thanks, > Nikolay
#1; a = 1; #0; a = 0; ...to do what you're trying to do, you need to put a zero delay in there in order to force the event list to be re-evaluated. This is standard verilog behavior. -t
