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Nikolay V. Pyatkov wrote:
| What should be the output of the program below in absolutely correct verilog
| simulator?
|
| Thanks,
| Nikolay
| module test_wait (/*AUTOARG*/ ) ;
| initial begin
| a = 0;
| forever begin
| wait (a == 1);
| $display ("in wait a = 1 at time %t", $time);
| wait (a == 0);
| $display ("in wait a = 0 at time %t", $time);
| end
| end
| initial begin
| #3; a = 1; a = 0;
| #1; a = 1; a = 0;
| #1; a = 1; a = 0;
| #1;
| $finish;
| end
|
| endmodule // test_wait
|
The a = 1; a = 0; runt pulse will not be caught by the "wait (a==1)"
because the wait needs to be scheculed between the two assignments,
and that won't happen. Therefire, a will always be 0 by the time the
wait checks, and it's stuck.
If you add #0 in front of the "a = 0" part, you'll see better
results (what VHDL folks call a "delta delay") but even that would
be somewhat prone to races. The wait really cannot be relied on for
detecting runt pulses. They need non-zero width, or you are going to
have various results from compiler to compiler.
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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