In ModelSim, If hdl is the directory you started ModelSim in, that is where it would look for include files by default.
It has a directive +incdir+ to tell it to also look in another directory. Here is a line from what I am working on now that shows how this works: vlog +incdir+../../../../../ftl_ddr2_phy_v1_00_a/hdl/verilog/../../../../../f tl_ddr2_phy_v1_00_a/hdl/verilog/ftl_ddr2_phy.v Do you have a road map of the features you will be adding to Icarus posted somewhere? We have started using more advanced features such as generate, SmartModels for Xilinx PPC and MGTs, and mixed Verilog and VHDL. Regards, John McCaskill Faster Technology LLC 1812 Avenue D, Suite 202, Katy, TX 77493 USA Tel: (281) 391-5482, Fax: (281) 391-9384 Email: [EMAIL PROTECTED] Web: http://www.fastertechnology.com > -----Original Message----- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf > Of Stephen Williams > Sent: Friday, February 03, 2006 2:24 PM > To: geda-dev > Subject: gEDA: Verilogrelative include path handling > > > This bug report: > > https://sourceforge.net/tracker/index.php?func=detail&aid=1412755&group_ id > =149850&atid=775997 > > Points out an issue with include files that has goon unnoticed by > me for a while. I've got 2 patches now to change the search behavior > for include files with relative paths, but I would like to get a > reading of what the rest of the world does before commiting. > > The example: > > hdl/a.v: > `include "b.v" > > hdl/b.v: > // some verilog code > > shell prompt: > iverilog hdl/a.v > > hdl/a.v:1348221540: Include file b.v not found > > So I take it this should work? What do other tools do here? I'm > inclined to apply a patch, but I just want to double-check with > other tools. > > -- > Steve Williams "The woods are lovely, dark and deep. > steve at icarus.com But I have promises to keep, > http://www.icarus.com and lines to code before I sleep, > http://www.picturel.com And lines to code before I sleep."
