On Fri, Feb 03, 2006 at 05:02:39PM -0600, John McCaskill wrote: > > generate ... Generate ... GENERATE !!!! > > Is this good or bad excitement?
Good excitement. I want it, and I'm happy when others say they do too. Right now the only bounty I can offer is a round of drinks at SV-OSEDA. I can't imagine the red tape I would have to jump through to get my lab to offer a bounty. Not to mention the red tape Steve would have to jump through to collect it. > I use Xilinx synthesis tools for FPGA design. > They added generate since I started using their tools. Me too^2. > I held off on using generate for a while to maximize how much code I could > simulate with Icarus. Now I am using it frequently, and it is very nice > to have. I have _still_ held off, but would very much like to use them in my designs. But not so much that I'm willing to abandon Icarus. > SmartModels are fast behavioral simulation models. For more information > see: > http://www.synopsys.com/products/lm/swmodel_ds.html Looks like alphabet soup, no source code or standards documents in sight. > I remember Steve mentioning that he was looking into them a while back. > Xilinx supplies SmartModels to allow you to simulate the embedded > PowerPCs in their FPGAs, and also to simulate the Multi-Gigabit > Transceivers (AKA SERDES blocks) in the FPGAs. > > We use both the PowerPCs and the MGTs in our designs, so I have to have > access to a simulator that supports them. Understood. Has anyone asked Xilinx if they can adapt their simulators to VPI/PLI? - Larry
