Christian Viller Hansen wrote:
Hi
I'm new to this list so forgive me if this topic is over and done with.
(I searched list and could not find recent threads concerning this.)
To be able to reuse schematics and layout between projects, it would be
great if it was possible to divide the project hierarchically in an easy
manner. I read in the gschem manual that you would have to create a
symbol with the correct name and place it with the schematics, but this
methodology might change later. This sounds reasonable, but not very
user-friendly. I haven't tried because I couldn't figure out how the
connectors should be created and so on. Would it be possible to have a
menu item that said "Make this schematic a symbol" and then have the
program figure out how many inputs and outputs you have on the
schematics and create the appropriate symbol?
Or maybe you could even mark a portion of you toplevel schematics and
"push" it down to a subschem?
I'll have to let someone who knows more about gschem and hierarchy speak
to this.
I have done some ASIC layout before and I like the way everything is a
cell and you don't need to draw a buffer every time you need one. It
would be nice to be able to do this seamlessly in pcb too. I see a few
issues that might need some clever thinking.
Refdes are unique in the netlist, but if you start adding a
bunch of copies of a schematics, you would either need to
regenerate refdes when you convert to netlist or refdes needs to
reflect their hierarchically context - could be something like
numbering the instances of subschems and put that in the name of
components R1_1 and R2_1 would point to the same resistor in two
different instances of the subschem, but then you get some very
ugly part-lists and you still need to teach pcb to support this
scheme. (It's no problem in layout because you just run LVS and
either it matches or it doesn't.)
Sometimes you might want to have a slightly different hierarchy
in pcb compared to schem, then all the ?.pcb.new stuff gets
really tricky. Maybe you can just sometimes ignore the ?.pcb.new
and rely on the netlist checker.
Should subcircuits/cells be mixed in between the components in
the lib toolbox?
gnetlist only sort of supports hierarchy in schematics right now. What
will happen is when you netlist, you will not be able to get a
hierarchical netlist but rather you will get a flat netlist for the
entire design. There is some processing of the refdes so that they all
end up being unique. Although now that I think about it I wonder if you
could come up with some examples that break[1].
pcb does not currently deal with hierarchy, but since gnetlist will
produce a flattened netlist this doesn't real matter except you may have
wanted to layout a subcircuit and instantiate it multiple times.
I would really like to see true hierarchical support added to gnetlist.
For driving spice or gnucap simulations thats really the right way to
do it.
Another thing I think could be really cool was a common techfile for the
projects. When I do pcb's I fabricate them on my own, so I need more
copper than most of the standard footprints provide. At some point I
might want to send my design to a professional and then I would need
different footprints and different drc rules. The techfile could contain
all the informations needed for a certain manufacturer and it might be a
convenient place to store paths and stuff to share between geda tools.
Some of the things I would store in the file:
drc rules, drill sizes, allowed grid snap sizes, path to footprints,
path to spice models, path to symbols, name of manufacturer and so on.
Some of this is in place. Look for "vendor resource file" in the pcb
manual. That lets you store drc rules and a list of drill sizes for a
particular vendor in a file. You can also load in that file and have
the drills in your design changed to use the available drill sizes.
There isn't currently something that points to a different footprint
directory though.
I hope I don't offend any of the hard working developers by thinking out
loud.
not at all.
True support for hierarchy is something I'd love to add both to gnetlist
and pcb, but I have a bunch of other projects to finish first.
-Dan
[1] I haven't looked at the exact form but I think gnetlist would take
something like I1/R2 (i.e. R2 inside of instance I1) and flatten it to
I1_R2. I wonder what would happen if you on purpose gave a refdes a
name like I1_R2 on something in the top level. I wonder if gnetlist
would be smart enough to catch that or not.
