Hi, I was just curios if anyone on list has used the open-cores cordic VHDL. I'm using it to generate a reference waveform for a PWM generator, and have been bashing my head against the wall with little oddities and glitches like different results for +ve and -ve angles (which should read the same for cosine).
Eventually, I tracked it down to the HDL which divides by a power of two in the cordic pipeline. Put simply... it doesn't work for -ve numbers. In twos complement - for the specific implementation used at least - which sign extends with the original MSB: -2 >> 1 == -1 -1 >> 1 == -1 (etc..) Clearly this is different from the behaviour for +ve numbers, hence he discrepency I noted. Does anyone per chance know an efficient hardware algorithm which can produce the same /2 results for +ve and -ve twos complement numbers? Depending on which stage in the cordic pipeline, the shift may be up to one less than a whole word length. I've no idea how this ends up being synthesised in an FPGA. My current work around is to test for negativity, take the -ve if it is -ve, (giving a +ve), do the shift, then take the -ve again (if the original was -ve). Perhaps the best way is for me to keep the cordic operating in the 0<->45 degree angle range, rather than the -45<->45 I've been using so far. Any thoughts? -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user