> tune down your edge rate in the FPGA to make the effective > bandwidth of your edges lower. square waves are an infinite series of sine > waves, trapezoidal are finite. ( roughly speaking ) > 3 inches is a 1/8th wave antenna for 500MHz, again roughly ( > 1GHz ~= > 12 inches ~=1 nS at the speed of light. ) > if you worried about signal integrity, ignore the logic analyzer
Yeah but on a pcb, flight-time on FR-4 is around 170pS / inch (off the top of my head, anyway). By way of 'rule of thumb' the trace looks like a transmission line if the flight time is greater than 1/4 wavelength. If 1ns edge rate, then it's 1/4 of 4nS, which translates into about 1" (I think I did that right). So anything longer than 1" will have transmission line affects, and you should consider termination. Xilinx fpga's are very capable of producing 1 nS edges or maybe better. That translates to around 500 MHz. My experience with the slew rate limiting on the spartan-2 is that it doesn't do very much. Dropping the drive strength will definitely slow the edges since the output impedance of the gate goes up and you get an RC rise time affect on the line. As long as the degraded rise-time is ok in your design, this is a good method. gene _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
