> Would like to find out what that iteration to get different > outputs is like. > > Is it like running the place and route pin mapping step for the > FPGA you're using > without changing the "synthesized" level of the design? > > John Griessen
OK, I was right, it is fpgaeditor. You will be using the 'probes' portion of it. Here's the run down: 1. write your code. 2. run synthesisis (XST) 3. run place and route 4. Open fpga editor. You can get to it from ISE by clicking the '+' under the map then select 'manually place' button. Alternatively, you launch fpga editor directly from a window browser or even from the command line. Your choice. 5. You need to open the design from within fpga editor. I ran a simple test using a 2 input, 1 output test case. The file was called simple.v so to open the design, I entered simple.ncd which you can browse to. 6. On the right hand side of the gui are a bunch of buttons. Look for the one that says 'probes'. Click it. 7. Use the 'add' button to add a new test point. 8. A popup becomes visible for 'define probe' 9. Select the net you wish to look at. 10. Select the pin you want it to go to, and press the ">" to actually make the selection active. 11. Press "OK". This returns you to the probes dialog box where you will see the net has been added, and they tell you what the delay will be in nS. 12. Press the 'bitgen' button, and you are all done. Use the newly created bit file to program your fpga. Lets say you want to remap the pin at a later time. Go back to the probes dialog box, select the signal you want to go, then choose 'delete'. That's it. Go back and remap it the way you want, re-gitgen and load it into the fpga. It's pretty simple once you try it. If you need some screen shots, I could probably provide some. gene _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
