Update... I'm still working on my SDRAM interface board: http://www.delorie.com/electronics/sdram/
I've been working on getting the sdram chip running at full speed (half speed works fine), so it's down to timing issues. I decided to remove the logic analyzer connector from the SDRAM side to clean up the signals (we've discussed this issue before), but I still need to debug the signals on that side. Plus, I need to check the relative timing of the read clock and the read data - i.e. the signals *inside* the chip. So, I decided to put a logic anaylzer *inside* the FPGA. It can watch the key signals at the right points, won't mess up the signal integrity, and I can get the data out on the MCU side anyway. The LA module I wrote is a DDR dual-bank capture, so it runs at 640 Ms/s (~1.5nS resolution), each sample 36 bits wide (this is limited by the small FPGA I chose), up to 1024 samples between the two banks. The MCU on the board reads the samples out through the mcu addr/data bus it already has with the FPGA and feeds the samples out over the USB. The console app I'm using on the PC to talk to the board sees the samples come across, and saves them to disk. A perl script turns them into a VCD file that gtkwave can read :-) Question: Can gtkwave be told to break up a bus into its component signals? My hardware LA can do this, it's really handy when you're trying to debug glitches relating to edge timing. _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user