Stephan Boettcher <boettc...@physik.uni-kiel.de> writes: > Thank you very much for you review! > > I need to go now, when I am back later today I will tell you what the > board is supposed to do.
I did not dare to ask for so detailed reviews of this board, I just wanted to present a test case where DRC either reports false positives, or is not helpfull enough to tell what actually is the problem. A small contribution towards improving the tool, which is, as mentioned, already amazingly good. But since you did look at the layout more closely, I guess the least I can do is to tell you what it is about. HISTORY ------- The board has a companion call IRENA which I develop in parallel, which in turn is the successor to a board the we have in use for a few years, called DIRENA. http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/irena/irena.pcb We want to sample signals from typically inhomgeniuos collections of silicon detectors, photo diodes and/or photo multiplier tubes, in setups or instruments for in situ radiation or energetic particle measurements in space. The charge sensitive preamplifiers are on an extra board or even inside the instrument under test. This is of course non-flight electronics, but is used to develop and test space-flight instruments. And now some of us want to fly it on ballon missions. These boards continuously sample the preamp outputs and do the trigger, pulse height reconstruction, peak detection ... digitally. I am actually spending some brain cycles on making this concept space-worthy (300 krad), but that is tough. ANALOG, input amps, ADCs ------------------------ The old DIRENA and the IRENA have 18 serial ADCs, AD7276 samling at 3MSPS. The ERENA, which is the board you looked at, has two AD9251 chips with two ADCs each, sampling at up to 80 MSPS. So it is four channels at 80MSPS. I have no idea how fast we can actually make it work. When both channels of a chip are used, the data is multiplexed to one digital output bus, on both edges of the data clock. The differential input amplifiers are AD8138s. This spring we only need to make the ERENA work with a single channel and maybe 24 MHz, for an instrument with a single PMT looking at two scintillators, and trying to separate the light from the different scintillators by the pulse shape. One scintillator ist fast (ns), the other is slower (us). The IRENA shall fly on a baloon with an instrument which was design for Mars, but got canceled. It's got nine silicon detectors. The premaps will deliver a dynamic range of 16 bit, so that each preamp output is feed to two shapers, one with unity gain and one with gain 16. The new IRENA has the shaping amplifiers in front of the 18 ADCs. The main reason to have them there is to isolate the front end from the clock feed through of the ADCs. The old DIRENA does not have them, since the shapers were integrated in the instrument that it was originally developed for. But we needed to add an additional board with linear amplifiers to not have the ADCs feed their clock back to the sensitve preamps. We hope we can avoid the extra amps this way. DIGITAL, FPGA, ARM7 ------------------- The central FPGA is an Altera Cyclon 3 (Cyclon II on the DIRENA). The back end is an ARM7 with built in USB slave. The old DIRENA is configured, controlled and read out via an opto-coupled parallel port, without any processor on the board. POWER, GROUNDING ---------------- Our engineer is developing a power and interface board (using proprietary EDA tools), with a(n ever growing :-) number of isolated power supplies, to accomodate the grounding. The connector to the front end delivers two or three voltages with separate return. This is on the frame on the signal layer that was mentioned. There is an analog return for the input amps and AD7276 ADCs. The power board delivers ±5.5V, and LDOs on the [IE]RENA boards provide what we actually need. The Altera gets 2.5V and 1.2V directly from the power board, again with a separate return, which has a low impedance connection to the analog return next to the ADCs. The ARM gets a 3.3V power directly from the power board, with a return that will _not_ be connected to the other returns, except though a resistor and protection diodes. I am thinking about 1kOhm, but that may be too much. High speed communication to the FPGA is via LVDS (SPI), but the configuration of the FPGA is single ended, which relies on that resistor for reference. But we can go pretty slow. The power and interface board has it's own secondary ground, which will also not get a low impedance connection to the ARM ground, but maybe 10 or even 100 Ohm. The USB ground will be connected to that power board ground, so that the externally connected computer systems are two steps removed from the analog ground. All boards will have a chassis ground plane and be mounted on frames to form Faraday cages between the boards, four separate compartments. At the front end we have the preamps (and detectors, in some use cases). The back sides of both the preamp and [IE]RENA boards, facing each other, will only have decoupled components, no signals, so that the compartment between front-end-board and [IE]RENA is pretty quiet. All analog grounds are tightly coupled to the chassis ground. The switching power supply is in the fourth compartment, far away from the front end. MISCELLANEOUS ------------- During the ballon flight, the data is recorded on a microSD card. A flash chip stores the FPGA and other configuration. The SD/flash SPI interface is also routed to the power connector, and there are plans to put an SPI to ethernet chip up there to send UDP packtes with the data to the ground during the flight, in case the hardware gets lost, as can happen with ballon missions. The [IE]RENA boards have a JTAG header for debugging the ARM. But normally, the flashing of the ARM firmware shall happen through an RS232 interface without having toopne the housing. The UART and associated reset/mode pins are routed to the power connector, the RS232 drivers are on the power board. Sometimes it is desirable to have an external trigger for the data acquisition setup. An LVDS input from the Altera is routed to the power board, where some driver can present an external trigger input. A 12 MHz oscillator drives both the ARM and the FPGA, the ARM will probably pll that up to 48 MHz or 60 MHz(max). The FPGA will run at 160 MHz (ERENA) or 192 MHz (IRENA) internally. I am sorry, this turned out to be rather longer than intended, but I will reuse it as an introduction to the documentation of this project :-) I'll stop now, else this text may grow even further. -- Stephan _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
