I see we are talking about two different things. I was responding to
Andrew's post about splitting nets into portions with different
properties. In my way of thinking if they have different properties,
they should be separate nets.
I see that your example of Power/Bypass we are talking about one net
with different properties. Ii think it will be hard to convey the
intricacies of power supply bypassing to an autorouter. One thing I
find interesting is how in an example you say the two subnets can
only join at P1. How do you define P1? To me this is the point
between two separate nets... which is really what you are
describing. The power net might be the copper plane layer of a PWB
while the Bypass net would be the short trace between a chip pin and
the cap. But where is P1? I have seen any number of discussions on
whether it is best to put the cap between the power plane via and the
chip or vice versa or if the power plane via can go between
them. Does P1 get defined in the schematic somehow or is this left
to the layout tool/person?
This can be discussed in theory, but until it can be mapped to
concrete examples of day to day use, I don't see the value. Do the
autorouters make use of any attributes like this? Is this something
that needs to be added to autorouters?
Rick
At 01:46 PM 8/15/2010, you wrote:
On Sun, 2010-08-15 at 12:36 -0400, Rick Collins wrote:
> And what will these subnets translate into in a layout tool? How
> would that translation be handled in the net list? A net is a net in
> my designs. If I have a "subnet" that I want handled differently
> from the rest of the net, that is not something that is added to a
> schematic because it is not related to the schematic. It is a layout
> issue and I address it in layout.
This is old workflow. You can go on using it, our indented changes will
allow it still, of course. It is fine for small boards, for low speed
design, for layouters who love to work hard and carefully...
For my 1000 parts DSO board I was not really happy with this strategy.
And I can not imagine that commercial EDA tools do not support the
layouter in a similar way as we now consider.
>
> How would you make use of "subnets" that would be useful that you
> can't do with just nets?
>
Maybe you missed some postings, and maybe my proposal:
http://ssalewski.de/gEDA-Netclass.html.en
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